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Commit 279b9e0c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux into drm-next 

more radeon fixes

* 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/dce8: workaround for atom BlankCrtc table
  drm/radeon/DCE4+: clear bios scratch dpms bit (v2)
  drm/radeon: set si_notify_smc_display_change properly
  drm/radeon: fix DAC interrupt handling on DCE5+
  drm/radeon: clean up active vram sizing
  drm/radeon: skip async dma init on r6xx
  drm/radeon/runpm: don't runtime suspend non-PX cards
  drm/radeon: add ring to fence trace functions
  drm/radeon: add missing trace point
  drm/radeon: fix VMID use tracking
parents 45ab1e07 78fe9e54

drivers/gpu/drm/radeon/atombios_crtc.c

+20 −0
Original line number Diff line number Diff line
@@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

}



static const u32 vga_control_regs[6] =

{

	AVIVO_D1VGA_CONTROL,

	AVIVO_D2VGA_CONTROL,

	EVERGREEN_D3VGA_CONTROL,

	EVERGREEN_D4VGA_CONTROL,

	EVERGREEN_D5VGA_CONTROL,

	EVERGREEN_D6VGA_CONTROL,

};



static void atombios_blank_crtc(struct drm_crtc *crtc, int state)

{

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 
	struct radeon_device *rdev = dev->dev_private;

	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);

	BLANK_CRTC_PS_ALLOCATION args;

	u32 vga_control = 0;



	memset(&args, 0, sizeof(args));



	if (ASIC_IS_DCE8(rdev)) {

		vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);

		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);

	}



	args.ucCRTC = radeon_crtc->crtc_id;

	args.ucBlanking = state;



	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);



	if (ASIC_IS_DCE8(rdev)) {

		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);

	}

}



static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)

drivers/gpu/drm/radeon/cik.c

+6 −0
Original line number Diff line number Diff line
@@ -3840,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable) 
	if (enable)

		WREG32(CP_ME_CNTL, 0);

	else {

		if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)

			radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	}
@@ -4038,6 +4040,10 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev) 
		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

		return r;

	}



	if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)

		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);



	return 0;

}

drivers/gpu/drm/radeon/cik_sdma.c

+6 −2
Original line number Diff line number Diff line
@@ -250,6 +250,8 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev) 
	u32 rb_cntl, reg_offset;

	int i;



	if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||

	    (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))

		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);



	for (i = 0; i < 2; i++) {
@@ -381,6 +383,8 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev) 
		}

	}



	if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||

	    (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))

		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);



	return 0;

drivers/gpu/drm/radeon/evergreen.c

+2 −2
Original line number Diff line number Diff line
@@ -4348,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	/* only one DAC on DCE6 */

	if (!ASIC_IS_DCE6(rdev))

	/* only one DAC on DCE5 */

	if (!ASIC_IS_DCE5(rdev))

		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

	WREG32(DACB_AUTODETECT_INT_CONTROL, 0);

drivers/gpu/drm/radeon/ni.c

+5 −1
Original line number Diff line number Diff line
@@ -1390,6 +1390,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 
	if (enable)

		WREG32(CP_ME_CNTL, 0);

	else {

		if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)

			radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

		WREG32(SCRATCH_UMSK, 0);
@@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev) 
		return r;

	}



	if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)

		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);



	return 0;

}