Loading arch/arm/mm/proc-v6.S +8 −1 Original line number Diff line number Diff line Loading @@ -55,7 +55,14 @@ ENTRY(cpu_v6_proc_init) mov pc, lr ENTRY(cpu_v6_proc_fin) mov pc, lr stmfd sp!, {lr} cpsid if @ disable interrupts bl v6_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches ldmfd sp!, {pc} /* * cpu_v6_reset(loc) Loading include/asm-arm/arch-pxa/pxa-regs.h +1 −1 Original line number Diff line number Diff line Loading @@ -653,7 +653,7 @@ #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ #define UDCCS_IO_DME (1 << 3) /* DMA enable */ #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ Loading Loading
arch/arm/mm/proc-v6.S +8 −1 Original line number Diff line number Diff line Loading @@ -55,7 +55,14 @@ ENTRY(cpu_v6_proc_init) mov pc, lr ENTRY(cpu_v6_proc_fin) mov pc, lr stmfd sp!, {lr} cpsid if @ disable interrupts bl v6_flush_kern_cache_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches ldmfd sp!, {pc} /* * cpu_v6_reset(loc) Loading
include/asm-arm/arch-pxa/pxa-regs.h +1 −1 Original line number Diff line number Diff line Loading @@ -653,7 +653,7 @@ #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ #define UDCCS_IO_DME (1 << 3) /* DMA enable */ #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ Loading