Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26a4f3c0 authored by Gleb Natapov's avatar Gleb Natapov Committed by Thomas Gleixner
Browse files

perf/x86: disable PEBS on a guest entry. 



If PMU counter has PEBS enabled it is not enough to disable counter
on a guest entry since PEBS memory write can overshoot guest entry
and corrupt guest memory. Disabling PEBS during guest entry solves
the problem.

Tested-by: default avatarDavid Ahern <dsahern@gmail.com>
Signed-off-by: default avatarGleb Natapov <gleb@redhat.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20120809085234.GI3341@redhat.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent cb37af77

arch/x86/kernel/cpu/perf_event_intel.c

+9 −1
Original line number Diff line number Diff line
@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 
	arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;

	arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;

	arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;

	/*

	 * If PMU counter has PEBS enabled it is not enough to disable counter

	 * on a guest entry since PEBS memory write can overshoot guest entry

	 * and corrupt guest memory. Disabling PEBS solves the problem.

	 */

	arr[1].msr = MSR_IA32_PEBS_ENABLE;

	arr[1].host = cpuc->pebs_enabled;

	arr[1].guest = 0;



	*nr = 1;

	*nr = 2;

	return arr;

}