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Commit 245c0278 authored by Jon Hunter's avatar Jon Hunter Committed by Greg Kroah-Hartman
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serial: tegra: Correct delay after TX flush 



For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 32 UART clock periods for the flush
to propagate otherwise TX data could be post. Add a helper function
to wait for N UART clock periods and update delay following FIFO
flush to be 32 UART clock cycles.

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7a7a7e6d

drivers/tty/serial/serial-tegra.c

+22 −2
Original line number Diff line number Diff line
@@ -234,6 +234,22 @@ static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 
	tup->lcr_shadow = lcr;

}



/**

 * tegra_uart_wait_cycle_time: Wait for N UART clock periods

 *

 * @tup:	Tegra serial port data structure.

 * @cycles:	Number of clock periods to wait.

 *

 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART

 * clock speed is 16X the current baud rate.

 */

static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,

				       unsigned int cycles)

{

	if (tup->current_baud)

		udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));

}



/* Wait for a symbol-time. */

static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,

		unsigned int syms)
@@ -263,8 +279,12 @@ static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 
	/* Dummy read to ensure the write is posted */

	tegra_uart_read(tup, UART_SCR);



	/* Wait for the flush to propagate. */

	tegra_uart_wait_sym_time(tup, 1);

	/*

	 * For all tegra devices (up to t210), there is a hardware issue that

	 * requires software to wait for 32 UART clock periods for the flush

	 * to propagate, otherwise data could be lost.

	 */

	tegra_uart_wait_cycle_time(tup, 32);

}



static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)