Merge branch 'security-fixes' into fixes (24195cad) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/Kconfig

+2 −1

Original line number	Diff line number	Diff line
		@@ -217,7 +217,8 @@ config VECTORS_BASE
		default DRAM_BASE if REMAP_VECTORS_TO_RAM
		default 0x00000000
		help
		The base address of exception vectors.
		The base address of exception vectors. This must be two pages
		in size.

		config ARM_PATCH_PHYS_VIRT
		bool "Patch physical to virtual translations at runtime" if EMBEDDED

arch/arm/include/asm/elf.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -130,4 +130,8 @@ struct mm_struct;
		extern unsigned long arch_randomize_brk(struct mm_struct *mm);
		#define arch_randomize_brk arch_randomize_brk

		#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
		struct linux_binprm;
		int arch_setup_additional_pages(struct linux_binprm *, int);

		#endif

arch/arm/include/asm/mmu.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@ typedef struct {
		int switch_pending;
		#endif
		unsigned int vmalloc_seq;
		unsigned long sigpage;
		} mm_context_t;

		#ifdef CONFIG_CPU_HAS_ASID

arch/arm/include/asm/page.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -142,7 +142,9 @@ extern void __cpu_copy_user_highpage(struct page to, struct page from,
		#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
		extern void copy_page(void to, const void from);

		#ifdef CONFIG_KUSER_HELPERS
		#define __HAVE_ARCH_GATE_AREA 1
		#endif

		#ifdef CONFIG_ARM_LPAE
		#include <asm/pgtable-3level-types.h>

arch/arm/kernel/entry-armv.S

+53 −50

Original line number	Diff line number	Diff line
		@@ -742,6 +742,18 @@ ENDPROC(__switch_to)
		#endif
		.endm

		.macro kuser_pad, sym, size
		.if (. - \sym) & 3
		.rept 4 - (. - \sym) & 3
		.byte 0
		.endr
		.endif
		.rept (\size - (. - \sym)) / 4
		.word 0xe7fddef1
		.endr
		.endm

		#ifdef CONFIG_KUSER_HELPERS
		.align 5
		.globl __kuser_helper_start
		__kuser_helper_start:
		@@ -832,18 +844,13 @@ kuser_cmpxchg64_fixup:
		#error "incoherent kernel configuration"
		#endif

		/* pad to next slot */
		.rept (16 - (. - __kuser_cmpxchg64)/4)
		.word 0
		.endr

		.align 5
		kuser_pad __kuser_cmpxchg64, 64

		__kuser_memory_barrier: @ 0xffff0fa0
		smp_dmb arm
		usr_ret lr

		.align 5
		kuser_pad __kuser_memory_barrier, 32

		__kuser_cmpxchg: @ 0xffff0fc0

		@@ -916,13 +923,14 @@ kuser_cmpxchg32_fixup:

		#endif

		.align 5
		kuser_pad __kuser_cmpxchg, 32

		__kuser_get_tls: @ 0xffff0fe0
		ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
		usr_ret lr
		mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
		.rep 4
		kuser_pad __kuser_get_tls, 16
		.rep 3
		.word 0 @ 0xffff0ff0 software TLS value, then
		.endr @ pad up to __kuser_helper_version

		@@ -932,14 +940,16 @@ __kuser_helper_version: @ 0xffff0ffc
		.globl __kuser_helper_end
		__kuser_helper_end:

		#endif

		THUMB( .thumb )

		/*
		* Vector stubs.
		*
		* This code is copied to 0xffff0200 so we can use branches in the
		* vectors, rather than ldr's. Note that this code must not
		* exceed 0x300 bytes.
		* This code is copied to 0xffff1000 so we can use branches in the
		* vectors, rather than ldr's. Note that this code must not exceed
		* a page size.
		*
		* Common stub entry macro:
		* Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
		@@ -986,8 +996,17 @@ ENDPROC(vector_\name)
		1:
		.endm

		.globl __stubs_start
		.section .stubs, "ax", %progbits
		__stubs_start:
		@ This must be the first word
		.word vector_swi

		vector_rst:
		ARM( swi SYS_ERROR0 )
		THUMB( svc #0 )
		THUMB( nop )
		b vector_und

		/*
		* Interrupt dispatcher
		*/
		@@ -1081,6 +1100,16 @@ __stubs_start:

		.align 5

		/*=============================================================================
		* Address exception handler
		*-----------------------------------------------------------------------------
		* These aren't too critical.
		* (they're not supposed to happen, and won't happen in 32-bit data mode).
		*/

		vector_addrexcptn:
		b vector_addrexcptn

		/*=============================================================================
		* Undefined FIQs
		*-----------------------------------------------------------------------------
		@@ -1094,45 +1123,19 @@ __stubs_start:
		vector_fiq:
		subs pc, lr, #4

		/*=============================================================================
		* Address exception handler
		*-----------------------------------------------------------------------------
		* These aren't too critical.
		* (they're not supposed to happen, and won't happen in 32-bit data mode).
		*/

		vector_addrexcptn:
		b vector_addrexcptn

		/*
		* We group all the following data together to optimise
		* for CPUs with separate I & D caches.
		*/
		.align 5

		.LCvswi:
		.word vector_swi

		.globl __stubs_end
		__stubs_end:

		.equ stubs_offset, __vectors_start + 0x200 - __stubs_start
		.globl vector_fiq_offset
		.equ vector_fiq_offset, vector_fiq

		.globl __vectors_start
		.section .vectors, "ax", %progbits
		__vectors_start:
		ARM( swi SYS_ERROR0 )
		THUMB( svc #0 )
		THUMB( nop )
		W(b) vector_und + stubs_offset
		W(ldr) pc, .LCvswi + stubs_offset
		W(b) vector_pabt + stubs_offset
		W(b) vector_dabt + stubs_offset
		W(b) vector_addrexcptn + stubs_offset
		W(b) vector_irq + stubs_offset
		W(b) vector_fiq + stubs_offset

		.globl __vectors_end
		__vectors_end:
		W(b) vector_rst
		W(b) vector_und
		W(ldr) pc, __vectors_start + 0x1000
		W(b) vector_pabt
		W(b) vector_dabt
		W(b) vector_addrexcptn
		W(b) vector_irq
		W(b) vector_fiq

		.data