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Commit 23c2b932 authored by Scott Telford's avatar Scott Telford Committed by Max Filippov
Browse files

xtensa: Added Cadence CSP kernel configuration for Xtensa 



Added defconfig, device tree and Xtensa variant header files for the
Cadence Configurable System Platform "xt_lnx" processor configuration.

Signed-off-by: default avatarScott Telford <stelford@cadence.com>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 73a3eed0

arch/xtensa/boot/dts/csp.dts

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/dts-v1/;



/ {

	compatible = "cdns,xtensa-xtfpga";

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&pic>;



	chosen {

		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk loglevel=8 nohz=off ignore_loglevel";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x40000000>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu@0 {

			compatible = "cdns,xtensa-cpu";

			reg = <0>;

		};

	};



	pic: pic {

		compatible = "cdns,xtensa-pic";

		#interrupt-cells = <2>;

		interrupt-controller;

	};



	clocks {

		osc: main-oscillator {

			#clock-cells = <0>;

			compatible = "fixed-clock";

		};

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		ranges = <0x00000000 0xf0000000 0x10000000>;



		uart0: serial@0d000000 {

			compatible = "xlnx,xuartps", "cdns,uart-r1p8";

			clocks = <&osc>, <&osc>;

			clock-names = "uart_clk", "pclk";

			reg = <0x0d000000 0x1000>;

			interrupts = <0 1>;

		};

	};

};

arch/xtensa/configs/cadence_csp_defconfig

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CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

CONFIG_USELIB=y

CONFIG_IRQ_DOMAIN_DEBUG=y

CONFIG_NO_HZ_IDLE=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IRQ_TIME_ACCOUNTING=y

CONFIG_BSD_PROCESS_ACCT=y

CONFIG_CGROUP_FREEZER=y

CONFIG_CPUSETS=y

CONFIG_CGROUP_DEVICE=y

CONFIG_CGROUP_CPUACCT=y

CONFIG_CGROUP_DEBUG=y

CONFIG_NAMESPACES=y

CONFIG_SCHED_AUTOGROUP=y

CONFIG_RELAY=y

CONFIG_BLK_DEV_INITRD=y

CONFIG_INITRAMFS_SOURCE="$$KERNEL_INITRAMFS_SOURCE"

# CONFIG_RD_BZIP2 is not set

# CONFIG_RD_LZMA is not set

# CONFIG_RD_XZ is not set

# CONFIG_RD_LZO is not set

# CONFIG_RD_LZ4 is not set

CONFIG_CC_OPTIMIZE_FOR_SIZE=y

CONFIG_SYSCTL_SYSCALL=y

CONFIG_EMBEDDED=y

CONFIG_PROFILING=y

CONFIG_MODULES=y

CONFIG_MODULE_FORCE_LOAD=y

CONFIG_MODULE_UNLOAD=y

CONFIG_MODULE_FORCE_UNLOAD=y

# CONFIG_IOSCHED_DEADLINE is not set

# CONFIG_IOSCHED_CFQ is not set

CONFIG_XTENSA_VARIANT_CUSTOM=y

CONFIG_XTENSA_VARIANT_CUSTOM_NAME="csp"

CONFIG_XTENSA_UNALIGNED_USER=y

CONFIG_PREEMPT=y

CONFIG_HIGHMEM=y

# CONFIG_PCI is not set

CONFIG_XTENSA_PLATFORM_XTFPGA=y

CONFIG_USE_OF=y

CONFIG_BUILTIN_DTB="csp"

# CONFIG_COMPACTION is not set

CONFIG_XTFPGA_LCD=y

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_IP_MULTICAST=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

CONFIG_IP_PNP_RARP=y

# CONFIG_INET_XFRM_MODE_TRANSPORT is not set

# CONFIG_INET_XFRM_MODE_TUNNEL is not set

# CONFIG_INET_XFRM_MODE_BEET is not set

# CONFIG_INET_DIAG is not set

# CONFIG_IPV6 is not set

# CONFIG_WIRELESS is not set

CONFIG_DEVTMPFS=y

CONFIG_DEVTMPFS_MOUNT=y

# CONFIG_STANDALONE is not set

# CONFIG_FW_LOADER is not set

CONFIG_MTD=y

CONFIG_MTD_CFI=y

CONFIG_MTD_JEDECPROBE=y

CONFIG_MTD_CFI_INTELEXT=y

CONFIG_MTD_CFI_AMDSTD=y

CONFIG_MTD_CFI_STAA=y

CONFIG_MTD_PHYSMAP_OF=y

CONFIG_MTD_UBI=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_RAM=y

CONFIG_SCSI=y

CONFIG_BLK_DEV_SD=y

# CONFIG_INPUT_MOUSEDEV is not set

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

CONFIG_LEGACY_PTY_COUNT=16

CONFIG_SERIAL_XILINX_PS_UART=y

CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y

CONFIG_HW_RANDOM=y

# CONFIG_HWMON is not set

CONFIG_WATCHDOG=y

CONFIG_WATCHDOG_NOWAYOUT=y

CONFIG_SOFT_WATCHDOG=y

# CONFIG_VGA_CONSOLE is not set

# CONFIG_USB_SUPPORT is not set

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_EXT3_FS=y

CONFIG_FANOTIFY=y

CONFIG_VFAT_FS=y

CONFIG_PROC_KCORE=y

CONFIG_TMPFS=y

CONFIG_TMPFS_POSIX_ACL=y

# CONFIG_MISC_FILESYSTEMS is not set

CONFIG_NFS_FS=y

CONFIG_NFS_V4=y

CONFIG_NFS_SWAP=y

CONFIG_ROOT_NFS=y

CONFIG_SUNRPC_DEBUG=y

CONFIG_NLS_CODEPAGE_437=y

CONFIG_NLS_ISO8859_1=y

CONFIG_PRINTK_TIME=y

CONFIG_DYNAMIC_DEBUG=y

CONFIG_DEBUG_INFO=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_LOCKUP_DETECTOR=y

# CONFIG_SCHED_DEBUG is not set

CONFIG_SCHEDSTATS=y

CONFIG_TIMER_STATS=y

CONFIG_DEBUG_RT_MUTEXES=y

CONFIG_PROVE_LOCKING=y

CONFIG_DEBUG_ATOMIC_SLEEP=y

CONFIG_RCU_TRACE=y

CONFIG_FUNCTION_TRACER=y

# CONFIG_S32C1I_SELFTEST is not set

# CONFIG_CRYPTO_ECHAINIV is not set

CONFIG_CRYPTO_DEFLATE=y

CONFIG_CRYPTO_LZO=y

# CONFIG_CRYPTO_HW is not set

arch/xtensa/variants/csp/include/variant/core.h

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File added.

Preview size limit exceeded, changes collapsed.

arch/xtensa/variants/csp/include/variant/tie-asm.h

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/* 

 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE

 *

 *  NOTE:  This header file is not meant to be included directly.

 */



/* This header file contains assembly-language definitions (assembly

   macros, etc.) for this specific Xtensa processor's TIE extensions

   and options.  It is customized to this Xtensa processor configuration.



   Copyright (c) 1999-2015 Cadence Design Systems Inc.



   Permission is hereby granted, free of charge, to any person obtaining

   a copy of this software and associated documentation files (the

   "Software"), to deal in the Software without restriction, including

   without limitation the rights to use, copy, modify, merge, publish,

   distribute, sublicense, and/or sell copies of the Software, and to

   permit persons to whom the Software is furnished to do so, subject to

   the following conditions:



   The above copyright notice and this permission notice shall be included

   in all copies or substantial portions of the Software.



   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */



#ifndef _XTENSA_CORE_TIE_ASM_H

#define _XTENSA_CORE_TIE_ASM_H



/*  Selection parameter values for save-area save/restore macros:  */

/*  Option vs. TIE:  */

#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */

#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */

#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */

/*  Whether used automatically by compiler:  */

#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */

#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */

#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */

/*  ABI handling across function calls:  */

#define XTHAL_SAS_CALR	0x0010	/* caller-saved */

#define XTHAL_SAS_CALE	0x0020	/* callee-saved */

#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */

#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */

/*  Misc  */

#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */

#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \

					| ((ccuse) & XTHAL_SAS_ANYCC)  \

					| ((abi)   & XTHAL_SAS_ANYABI) )





    /*

      *  Macro to store all non-coprocessor (extra) custom TIE and optional state

      *  (not including zero-overhead loop registers).

      *  Required parameters:

      *      ptr         Save area pointer address register (clobbered)

      *                  (register must contain a 4 byte aligned address).

      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS

      *                  registers are clobbered, the remaining are unused).

      *  Optional parameters:

      *      continue    If macro invoked as part of a larger store sequence, set to 1

      *                  if this is not the first in the sequence.  Defaults to 0.

      *      ofs         Offset from start of larger sequence (from value of first ptr

      *                  in sequence) at which to store.  Defaults to next available space

      *                  (or 0 if <continue> is 0).

      *      select      Select what category(ies) of registers to store, as a bitmask

      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.

      *      alloc       Select what category(ies) of registers to allocate; if any

      *                  category is selected here that is not in <select>, space for

      *                  the corresponding registers is skipped without doing any store.

      */

    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0

	xchal_sa_start	\continue, \ofs

	// Optional global registers used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)

	xchal_sa_align	\ptr, 0, 1020, 4, 4

	rur.THREADPTR	\at1		// threadptr option

	s32i	\at1, \ptr, .Lxchal_ofs_+0

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1020, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4

	.endif

	// Optional caller-saved registers used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)

	xchal_sa_align	\ptr, 0, 1016, 4, 4

	rsr.ACCLO	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+0

	rsr.ACCHI	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1016, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8

	.endif

	// Optional caller-saved registers not used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)

	xchal_sa_align	\ptr, 0, 1000, 4, 4

	rsr.BR	\at1		// boolean option

	s32i	\at1, \ptr, .Lxchal_ofs_+0

	rsr.SCOMPARE1	\at1		// conditional store option

	s32i	\at1, \ptr, .Lxchal_ofs_+4

	rsr.M0	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+8

	rsr.M1	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+12

	rsr.M2	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+16

	rsr.M3	\at1		// MAC16 option

	s32i	\at1, \ptr, .Lxchal_ofs_+20

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1000, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24

	.endif

    .endm	// xchal_ncp_store



    /*

      *  Macro to load all non-coprocessor (extra) custom TIE and optional state

      *  (not including zero-overhead loop registers).

      *  Required parameters:

      *      ptr         Save area pointer address register (clobbered)

      *                  (register must contain a 4 byte aligned address).

      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS

      *                  registers are clobbered, the remaining are unused).

      *  Optional parameters:

      *      continue    If macro invoked as part of a larger load sequence, set to 1

      *                  if this is not the first in the sequence.  Defaults to 0.

      *      ofs         Offset from start of larger sequence (from value of first ptr

      *                  in sequence) at which to load.  Defaults to next available space

      *                  (or 0 if <continue> is 0).

      *      select      Select what category(ies) of registers to load, as a bitmask

      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.

      *      alloc       Select what category(ies) of registers to allocate; if any

      *                  category is selected here that is not in <select>, space for

      *                  the corresponding registers is skipped without doing any load.

      */

    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0

	xchal_sa_start	\continue, \ofs

	// Optional global registers used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)

	xchal_sa_align	\ptr, 0, 1020, 4, 4

	l32i	\at1, \ptr, .Lxchal_ofs_+0

	wur.THREADPTR	\at1		// threadptr option

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1020, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4

	.endif

	// Optional caller-saved registers used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)

	xchal_sa_align	\ptr, 0, 1016, 4, 4

	l32i	\at1, \ptr, .Lxchal_ofs_+0

	wsr.ACCLO	\at1		// MAC16 option

	l32i	\at1, \ptr, .Lxchal_ofs_+4

	wsr.ACCHI	\at1		// MAC16 option

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1016, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8

	.endif

	// Optional caller-saved registers not used by default by the compiler:

	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)

	xchal_sa_align	\ptr, 0, 1000, 4, 4

	l32i	\at1, \ptr, .Lxchal_ofs_+0

	wsr.BR	\at1		// boolean option

	l32i	\at1, \ptr, .Lxchal_ofs_+4

	wsr.SCOMPARE1	\at1		// conditional store option

	l32i	\at1, \ptr, .Lxchal_ofs_+8

	wsr.M0	\at1		// MAC16 option

	l32i	\at1, \ptr, .Lxchal_ofs_+12

	wsr.M1	\at1		// MAC16 option

	l32i	\at1, \ptr, .Lxchal_ofs_+16

	wsr.M2	\at1		// MAC16 option

	l32i	\at1, \ptr, .Lxchal_ofs_+20

	wsr.M3	\at1		// MAC16 option

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24

	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0

	xchal_sa_align	\ptr, 0, 1000, 4, 4

	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24

	.endif

    .endm	// xchal_ncp_load





#define XCHAL_NCP_NUM_ATMPS	1



#define XCHAL_SA_NUM_ATMPS	1



#endif /*_XTENSA_CORE_TIE_ASM_H*/

arch/xtensa/variants/csp/include/variant/tie.h

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/* 

 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration

 *

 *  NOTE:  This header file is not meant to be included directly.

 */



/* This header file describes this specific Xtensa processor's TIE extensions

   that extend basic Xtensa core functionality.  It is customized to this

   Xtensa processor configuration.



   Copyright (c) 1999-2015 Cadence Design Systems Inc.



   Permission is hereby granted, free of charge, to any person obtaining

   a copy of this software and associated documentation files (the

   "Software"), to deal in the Software without restriction, including

   without limitation the rights to use, copy, modify, merge, publish,

   distribute, sublicense, and/or sell copies of the Software, and to

   permit persons to whom the Software is furnished to do so, subject to

   the following conditions:



   The above copyright notice and this permission notice shall be included

   in all copies or substantial portions of the Software.



   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */



#ifndef _XTENSA_CORE_TIE_H

#define _XTENSA_CORE_TIE_H



#define XCHAL_CP_NUM			1	/* number of coprocessors */

#define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */

#define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */

#define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */



/*  Basic parameters of each coprocessor:  */

#define XCHAL_CP7_NAME			"XTIOP"

#define XCHAL_CP7_IDENT			XTIOP

#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */

#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */

#define XCHAL_CP_ID_XTIOP           	7	/* coprocessor ID (0..7) */



/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */

#define XCHAL_CP0_SA_SIZE		0

#define XCHAL_CP0_SA_ALIGN		1

#define XCHAL_CP1_SA_SIZE		0

#define XCHAL_CP1_SA_ALIGN		1

#define XCHAL_CP2_SA_SIZE		0

#define XCHAL_CP2_SA_ALIGN		1

#define XCHAL_CP3_SA_SIZE		0

#define XCHAL_CP3_SA_ALIGN		1

#define XCHAL_CP4_SA_SIZE		0

#define XCHAL_CP4_SA_ALIGN		1

#define XCHAL_CP5_SA_SIZE		0

#define XCHAL_CP5_SA_ALIGN		1

#define XCHAL_CP6_SA_SIZE		0

#define XCHAL_CP6_SA_ALIGN		1



/*  Save area for non-coprocessor optional and custom (TIE) state:  */

#define XCHAL_NCP_SA_SIZE		36

#define XCHAL_NCP_SA_ALIGN		4



/*  Total save area for optional and custom state (NCP + CPn):  */

#define XCHAL_TOTAL_SA_SIZE		48	/* with 16-byte align padding */

#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */



/*

 * Detailed contents of save areas.

 * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)

 * before expanding the XCHAL_xxx_SA_LIST() macros.

 *

 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,

 *		dbnum,base,regnum,bitsz,gapsz,reset,x...)

 *

 *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand

 *	ccused = set if used by compiler without special options or code

 *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)

 *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)

 *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)

 *	name = lowercase reg name (no quotes)

 *	galign = group byte alignment (power of 2) (galign >= align)

 *	align = register byte alignment (power of 2)

 *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)

 *	  (not including any pad bytes required to galign this or next reg)

 *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)

 *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)

 *	regnum = reg index in regfile, or special/TIE-user reg number

 *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)

 *	gapsz = intervening bits, if bitsz bits not stored contiguously

 *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)

 *	reset = register reset value (or 0 if undefined at reset)

 *	x = reserved for future use (0 until then)

 *

 *  To filter out certain registers, e.g. to expand only the non-global

 *  registers used by the compiler, you can do something like this:

 *

 *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)

 *  #define SELCC0(p...)

 *  #define SELCC1(abikind,p...)	SELAK##abikind(p)

 *  #define SELAK0(p...)		REG(p)

 *  #define SELAK1(p...)		REG(p)

 *  #define SELAK2(p...)

 *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \

 *		...what you want to expand...

 */



#define XCHAL_NCP_SA_NUM	9

#define XCHAL_NCP_SA_LIST(s)	\

 XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \

 XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \

 XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \

 XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0)



#define XCHAL_CP0_SA_NUM	0

#define XCHAL_CP0_SA_LIST(s)	/* empty */



#define XCHAL_CP1_SA_NUM	0

#define XCHAL_CP1_SA_LIST(s)	/* empty */



#define XCHAL_CP2_SA_NUM	0

#define XCHAL_CP2_SA_LIST(s)	/* empty */



#define XCHAL_CP3_SA_NUM	0

#define XCHAL_CP3_SA_LIST(s)	/* empty */



#define XCHAL_CP4_SA_NUM	0

#define XCHAL_CP4_SA_LIST(s)	/* empty */



#define XCHAL_CP5_SA_NUM	0

#define XCHAL_CP5_SA_LIST(s)	/* empty */



#define XCHAL_CP6_SA_NUM	0

#define XCHAL_CP6_SA_LIST(s)	/* empty */



#define XCHAL_CP7_SA_NUM	0

#define XCHAL_CP7_SA_LIST(s)	/* empty */



/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */

#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3

/* Byte length of instruction from its first byte, per FLIX.  */

#define XCHAL_BYTE0_FORMAT_LENGTHS	\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\

	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3



#endif /*_XTENSA_CORE_TIE_H*/