Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 22c01cc4 authored by Anatoli Antonovitch's avatar Anatoli Antonovitch Committed by Alex Deucher
Browse files

drm/amdgpu: execution barrier after fence v2 



Insert wait for reg mem after EOP to fix potential issue with vm context switch

v2: move wait to vm_flush() use equal instead of greater than.

Signed-off-by: default avatarAnatoli Antonovitch <anatoli.antonovitch@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3daea9e3

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+12 −0
Original line number Diff line number Diff line
@@ -3965,6 +3965,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 
			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));

	amdgpu_ring_write(ring, lower_32_bits(seq));

	amdgpu_ring_write(ring, upper_32_bits(seq));



}



/**
@@ -4044,6 +4045,17 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
					unsigned vm_id, uint64_t pd_addr)

{

	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);

	uint32_t seq = ring->fence_drv.sync_seq[ring->idx];

	uint64_t addr = ring->fence_drv.gpu_addr;



	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */

		 WAIT_REG_MEM_FUNCTION(3))); /* equal */

	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq);

	amdgpu_ring_write(ring, 0xffffffff);

	amdgpu_ring_write(ring, 4); /* poll interval */



	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |