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Commit 22260139 authored by Emilio López's avatar Emilio López Committed by Mike Turquette
Browse files

clk: sunxi: fix some calculations 



Some divisor calculations were misrounded, causing higher than requested
rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one
homebrew instance of it as well with the right macro.

Reported-by: default avatarBoris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 5a8ddf26

drivers/clk/sunxi/clk-sunxi.c

+3 −3
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, 
	if (parent_rate < *freq)

		*freq = parent_rate;



	parent_rate = (parent_rate + (*freq - 1)) / *freq;

	parent_rate = DIV_ROUND_UP(parent_rate, *freq);



	/* Invalid rate! */

	if (parent_rate > 32)
@@ -344,7 +344,7 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, 
	if (*freq > parent_rate)

		*freq = parent_rate;



	div = parent_rate / *freq;

	div = DIV_ROUND_UP(parent_rate, *freq);



	if (div < 16)

		calcp = 0;
@@ -385,7 +385,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, 
	if (*freq > parent_rate)

		*freq = parent_rate;



	div = parent_rate / *freq;

	div = DIV_ROUND_UP(parent_rate, *freq);



	if (div < 32)

		calcp = 0;