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Commit 21e20e22 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux 

Pull clock fixes from Mike Turquette:
 "Late fixes for clock drivers.  All of these fixes are for user-visible
  regressions, typically boot failures or other unsafe system
  configuration that causes badness"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: clk-divider: fix divisor > 255 bug
  clk: exynos: File scope reg_save array should depend on PM_SLEEP
  clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
  ARM: dts: exynos5250: Fix MDMA0 clock number
  clk: samsung: exynos5250: Add MDMA0 clocks
  clk: samsung: exynos5250: Fix ACP gate register offset
  clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
  clk: samsung: exynos4: Correct SRC_MFC register
parents 2aa63ce0 778037e1

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

+2 −0
Original line number Diff line number Diff line
@@ -159,6 +159,8 @@ clock which they consume. 
  mixer			343

  hdmi			344

  g2d			345

  mdma0			346

  smmu_mdma0		347





   [Clock Muxes]

arch/arm/boot/dts/exynos5250.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -559,7 +559,7 @@ 
			compatible = "arm,pl330", "arm,primecell";

			reg = <0x10800000 0x1000>;

			interrupts = <0 33 0>;

			clocks = <&clock 271>;

			clocks = <&clock 346>;

			clock-names = "apb_pclk";

			#dma-cells = <1>;

			#dma-channels = <8>;

drivers/clk/clk-divider.c

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table, 
	return 0;

}



static unsigned int _get_val(struct clk_divider *divider, u8 div)

static unsigned int _get_val(struct clk_divider *divider, unsigned int div)

{

	if (divider->flags & CLK_DIVIDER_ONE_BASED)

		return div;

drivers/clk/samsung/clk-exynos-audss.c

+5 −5
Original line number Diff line number Diff line
@@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data; 
#define ASS_CLK_DIV 0x4

#define ASS_CLK_GATE 0x8



/* list of all parent clock list */

static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };

static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };



#ifdef CONFIG_PM_SLEEP

static unsigned long reg_save[][2] = {

	{ASS_CLK_SRC,  0},

	{ASS_CLK_DIV,  0},

	{ASS_CLK_GATE, 0},

};



/* list of all parent clock list */

static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };

static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };



#ifdef CONFIG_PM_SLEEP

static int exynos_audss_clk_suspend(void)

{

	int i;

drivers/clk/samsung/clk-exynos4.c

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#define SRC_TOP1		0xc214

#define SRC_CAM			0xc220

#define SRC_TV			0xc224

#define SRC_MFC			0xcc28

#define SRC_MFC			0xc228

#define SRC_G3D			0xc22c

#define E4210_SRC_IMAGE		0xc230

#define SRC_LCD0		0xc234