Loading include/asm-xtensa/byteorder.h +15 −17 Original line number Original line Diff line number Diff line Loading @@ -14,7 +14,17 @@ #include <asm/types.h> #include <asm/types.h> #include <linux/compiler.h> #include <linux/compiler.h> static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) #ifdef __XTENSA_EL__ # define __LITTLE_ENDIAN #elif defined(__XTENSA_EB__) # define __BIG_ENDIAN #else # error processor byte order undefined! #endif #define __SWAB_64_THRU_32__ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { { __u32 res; __u32 res; /* instruction sequence from Xtensa ISA release 2/2000 */ /* instruction sequence from Xtensa ISA release 2/2000 */ Loading @@ -28,8 +38,9 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) ); ); return res; return res; } } #define __arch_swab32 __arch_swab32 static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { { /* Given that 'short' values are signed (i.e., can be negative), /* Given that 'short' values are signed (i.e., can be negative), * we cannot assume that the upper 16-bits of the register are * we cannot assume that the upper 16-bits of the register are Loading Loading @@ -62,21 +73,8 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return res; return res; } } #define __arch_swab16 __arch_swab16 #define __arch__swab32(x) ___arch__swab32(x) #include <linux/byteorder.h> #define __arch__swab16(x) ___arch__swab16(x) #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ #endif #ifdef __XTENSA_EL__ # include <linux/byteorder/little_endian.h> #elif defined(__XTENSA_EB__) # include <linux/byteorder/big_endian.h> #else # error processor byte order undefined! #endif #endif /* _XTENSA_BYTEORDER_H */ #endif /* _XTENSA_BYTEORDER_H */ Loading
include/asm-xtensa/byteorder.h +15 −17 Original line number Original line Diff line number Diff line Loading @@ -14,7 +14,17 @@ #include <asm/types.h> #include <asm/types.h> #include <linux/compiler.h> #include <linux/compiler.h> static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) #ifdef __XTENSA_EL__ # define __LITTLE_ENDIAN #elif defined(__XTENSA_EB__) # define __BIG_ENDIAN #else # error processor byte order undefined! #endif #define __SWAB_64_THRU_32__ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { { __u32 res; __u32 res; /* instruction sequence from Xtensa ISA release 2/2000 */ /* instruction sequence from Xtensa ISA release 2/2000 */ Loading @@ -28,8 +38,9 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) ); ); return res; return res; } } #define __arch_swab32 __arch_swab32 static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { { /* Given that 'short' values are signed (i.e., can be negative), /* Given that 'short' values are signed (i.e., can be negative), * we cannot assume that the upper 16-bits of the register are * we cannot assume that the upper 16-bits of the register are Loading Loading @@ -62,21 +73,8 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return res; return res; } } #define __arch_swab16 __arch_swab16 #define __arch__swab32(x) ___arch__swab32(x) #include <linux/byteorder.h> #define __arch__swab16(x) ___arch__swab16(x) #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ #endif #ifdef __XTENSA_EL__ # include <linux/byteorder/little_endian.h> #elif defined(__XTENSA_EB__) # include <linux/byteorder/big_endian.h> #else # error processor byte order undefined! #endif #endif /* _XTENSA_BYTEORDER_H */ #endif /* _XTENSA_BYTEORDER_H */