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Commit 204b7793 authored by Xenia Ragiadakou's avatar Xenia Ragiadakou Committed by Sarah Sharp
Browse files

xhci: replace xhci_writel() with writel() 



Function xhci_writel() is used to write a 32bit value in xHC registers residing
in MMIO address space. It takes as first argument a pointer to the xhci_hcd
although it does not use it. xhci_writel() internally simply calls writel().
This creates an illusion that xhci_writel() is an xhci specific function that
has to be called in a context where a pointer to xhci_hcd is available.

Remove xhci_writel() wrapper function and replace its calls with calls to
writel() to make the code more straight-forward.

Signed-off-by: default avatarXenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
parent b0ba9720

drivers/usb/host/xhci-hub.c

+16 −19
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 
	}



	/* Write 1 to disable the port */

	xhci_writel(xhci, port_status | PORT_PE, addr);

	writel(port_status | PORT_PE, addr);

	port_status = readl(addr);

	xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",

			wIndex, port_status);
@@ -388,7 +388,7 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 
		return;

	}

	/* Change bits are all write 1 to clear */

	xhci_writel(xhci, port_status | status, addr);

	writel(port_status | status, addr);

	port_status = readl(addr);

	xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",

			port_change_bit, wIndex, port_status);
@@ -419,7 +419,7 @@ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 
	temp = xhci_port_state_to_neutral(temp);

	temp &= ~PORT_PLS_MASK;

	temp |= PORT_LINK_STROBE | link_state;

	xhci_writel(xhci, temp, port_array[port_id]);

	writel(temp, port_array[port_id]);

}



static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
@@ -445,7 +445,7 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 
	else

		temp &= ~PORT_WKOC_E;



	xhci_writel(xhci, temp, port_array[port_id]);

	writel(temp, port_array[port_id]);

}



/* Test and clear port RWC bit */
@@ -458,7 +458,7 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 
	if (temp & port_bit) {

		temp = xhci_port_state_to_neutral(temp);

		temp |= port_bit;

		xhci_writel(xhci, temp, port_array[port_id]);

		writel(temp, port_array[port_id]);

	}

}
@@ -838,8 +838,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
				temp |= PORT_CSC | PORT_PEC | PORT_WRC |

					PORT_OCC | PORT_RC | PORT_PLC |

					PORT_CEC;

				xhci_writel(xhci, temp | PORT_PE,

					port_array[wIndex]);

				writel(temp | PORT_PE, port_array[wIndex]);

				temp = readl(port_array[wIndex]);

				break;

			}
@@ -894,8 +893,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
			 * However, khubd will ignore the roothub events until

			 * the roothub is registered.

			 */

			xhci_writel(xhci, temp | PORT_POWER,

					port_array[wIndex]);

			writel(temp | PORT_POWER, port_array[wIndex]);



			temp = readl(port_array[wIndex]);

			xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
@@ -910,7 +908,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
			break;

		case USB_PORT_FEAT_RESET:

			temp = (temp | PORT_RESET);

			xhci_writel(xhci, temp, port_array[wIndex]);

			writel(temp, port_array[wIndex]);



			temp = readl(port_array[wIndex]);

			xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
@@ -925,7 +923,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
			break;

		case USB_PORT_FEAT_BH_PORT_RESET:

			temp |= PORT_WR;

			xhci_writel(xhci, temp, port_array[wIndex]);

			writel(temp, port_array[wIndex]);



			temp = readl(port_array[wIndex]);

			break;
@@ -935,7 +933,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
			temp = readl(port_array[wIndex] + PORTPMSC);

			temp &= ~PORT_U1_TIMEOUT_MASK;

			temp |= PORT_U1_TIMEOUT(timeout);

			xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);

			writel(temp, port_array[wIndex] + PORTPMSC);

			break;

		case USB_PORT_FEAT_U2_TIMEOUT:

			if (hcd->speed != HCD_USB3)
@@ -943,7 +941,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
			temp = readl(port_array[wIndex] + PORTPMSC);

			temp &= ~PORT_U2_TIMEOUT_MASK;

			temp |= PORT_U2_TIMEOUT(timeout);

			xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);

			writel(temp, port_array[wIndex] + PORTPMSC);

			break;

		default:

			goto error;
@@ -1007,8 +1005,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 
					port_array[wIndex], temp);

			break;

		case USB_PORT_FEAT_POWER:

			xhci_writel(xhci, temp & ~PORT_POWER,

				port_array[wIndex]);

			writel(temp & ~PORT_POWER, port_array[wIndex]);



			spin_unlock_irqrestore(&xhci->lock, flags);

			temp = usb_acpi_power_manageable(hcd->self.root_hub,
@@ -1156,7 +1153,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd) 


		t1 = xhci_port_state_to_neutral(t1);

		if (t1 != t2)

			xhci_writel(xhci, t2, port_array[port_index]);

			writel(t2, port_array[port_index]);

	}

	hcd->state = HC_STATE_SUSPENDED;

	bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
@@ -1188,7 +1185,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
	/* delay the irqs */

	temp = readl(&xhci->op_regs->command);

	temp &= ~CMD_EIE;

	xhci_writel(xhci, temp, &xhci->op_regs->command);

	writel(temp, &xhci->op_regs->command);



	port_index = max_ports;

	while (port_index--) {
@@ -1234,7 +1231,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
			if (slot_id)

				xhci_ring_device(xhci, slot_id);

		} else

			xhci_writel(xhci, temp, port_array[port_index]);

			writel(temp, port_array[port_index]);

	}



	(void) readl(&xhci->op_regs->command);
@@ -1243,7 +1240,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
	/* re-enable irqs */

	temp = readl(&xhci->op_regs->command);

	temp |= CMD_EIE;

	xhci_writel(xhci, temp, &xhci->op_regs->command);

	writel(temp, &xhci->op_regs->command);

	temp = readl(&xhci->op_regs->command);



	spin_unlock_irqrestore(&xhci->lock, flags);

drivers/usb/host/xhci-mem.c

+3 −3
Original line number Diff line number Diff line
@@ -2254,7 +2254,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
	val |= (val2 & ~HCS_SLOTS_MASK);

	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Setting Max device slots reg = 0x%x.", val);

	xhci_writel(xhci, val, &xhci->op_regs->config_reg);

	writel(val, &xhci->op_regs->config_reg);



	/*

	 * Section 5.4.8 - doorbell array must be
@@ -2388,7 +2388,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Write ERST size = %i to ir_set 0 (some bits preserved)",

			val);

	xhci_writel(xhci, val, &xhci->ir_set->erst_size);

	writel(val, &xhci->ir_set->erst_size);



	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Set ERST entries to point to event ring.");
@@ -2434,7 +2434,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
	temp = readl(&xhci->op_regs->dev_notification);

	temp &= ~DEV_NOTE_MASK;

	temp |= DEV_NOTE_FWAKE;

	xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);

	writel(temp, &xhci->op_regs->dev_notification);



	return 0;

drivers/usb/host/xhci-ring.c

+4 −4
Original line number Diff line number Diff line
@@ -295,7 +295,7 @@ void xhci_ring_cmd_db(struct xhci_hcd *xhci) 
		return;



	xhci_dbg(xhci, "// Ding dong!\n");

	xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);

	writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);

	/* Flush PCI posted writes */

	readl(&xhci->dba->doorbell[0]);

}
@@ -427,7 +427,7 @@ void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 
	if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||

	    (ep_state & EP_HALTED))

		return;

	xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);

	writel(DB_VALUE(ep_index, stream_id), db_addr);

	/* The CPU has better things to do at this point than wait for a

	 * write-posting flush.  It'll get there soon enough.

	 */
@@ -2853,7 +2853,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) 
	 * Write 1 to clear the interrupt status.

	 */

	status |= STS_EINT;

	xhci_writel(xhci, status, &xhci->op_regs->status);

	writel(status, &xhci->op_regs->status);

	/* FIXME when MSI-X is supported and there are multiple vectors */

	/* Clear the MSI-X event interrupt status */
@@ -2862,7 +2862,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) 
		/* Acknowledge the PCI interrupt */

		irq_pending = readl(&xhci->ir_set->irq_pending);

		irq_pending |= IMAN_IP;

		xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);

		writel(irq_pending, &xhci->ir_set->irq_pending);

	}



	if (xhci->xhc_state & XHCI_STATE_DYING) {

drivers/usb/host/xhci.c

+24 −27
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ void xhci_quiesce(struct xhci_hcd *xhci) 


	cmd = readl(&xhci->op_regs->command);

	cmd &= mask;

	xhci_writel(xhci, cmd, &xhci->op_regs->command);

	writel(cmd, &xhci->op_regs->command);

}



/*
@@ -128,7 +128,7 @@ static int xhci_start(struct xhci_hcd *xhci) 
	temp |= (CMD_RUN);

	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",

			temp);

	xhci_writel(xhci, temp, &xhci->op_regs->command);

	writel(temp, &xhci->op_regs->command);



	/*

	 * Wait for the HCHalted Status bit to be 0 to indicate the host is
@@ -167,7 +167,7 @@ int xhci_reset(struct xhci_hcd *xhci) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");

	command = readl(&xhci->op_regs->command);

	command |= CMD_RESET;

	xhci_writel(xhci, command, &xhci->op_regs->command);

	writel(command, &xhci->op_regs->command);



	ret = xhci_handshake(xhci, &xhci->op_regs->command,

			CMD_RESET, 0, 10 * 1000 * 1000);
@@ -614,21 +614,20 @@ int xhci_run(struct usb_hcd *hcd) 
	temp = readl(&xhci->ir_set->irq_control);

	temp &= ~ER_IRQ_INTERVAL_MASK;

	temp |= (u32) 160;

	xhci_writel(xhci, temp, &xhci->ir_set->irq_control);

	writel(temp, &xhci->ir_set->irq_control);



	/* Set the HCD state before we enable the irqs */

	temp = readl(&xhci->op_regs->command);

	temp |= (CMD_EIE);

	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Enable interrupts, cmd = 0x%x.", temp);

	xhci_writel(xhci, temp, &xhci->op_regs->command);

	writel(temp, &xhci->op_regs->command);



	temp = readl(&xhci->ir_set->irq_pending);

	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Enabling event ring interrupter %p by writing 0x%x to irq_pending",

			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));

	xhci_writel(xhci, ER_IRQ_ENABLE(temp),

			&xhci->ir_set->irq_pending);

	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);

	xhci_print_ir_set(xhci, 0);



	if (xhci->quirks & XHCI_NEC_HOST)
@@ -699,10 +698,9 @@ void xhci_stop(struct usb_hcd *hcd) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Disabling event ring interrupts");

	temp = readl(&xhci->op_regs->status);

	xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);

	writel(temp & ~STS_EINT, &xhci->op_regs->status);

	temp = readl(&xhci->ir_set->irq_pending);

	xhci_writel(xhci, ER_IRQ_DISABLE(temp),

			&xhci->ir_set->irq_pending);

	writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);

	xhci_print_ir_set(xhci, 0);



	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
@@ -762,15 +760,15 @@ static void xhci_save_registers(struct xhci_hcd *xhci) 


static void xhci_restore_registers(struct xhci_hcd *xhci)

{

	xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);

	xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);

	writel(xhci->s3.command, &xhci->op_regs->command);

	writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);

	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);

	xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);

	xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);

	writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);

	writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);

	xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);

	xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);

	xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);

	xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);

	writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);

	writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);

}



static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
@@ -868,7 +866,7 @@ int xhci_suspend(struct xhci_hcd *xhci) 
	/* step 2: clear Run/Stop bit */

	command = readl(&xhci->op_regs->command);

	command &= ~CMD_RUN;

	xhci_writel(xhci, command, &xhci->op_regs->command);

	writel(command, &xhci->op_regs->command);



	/* Some chips from Fresco Logic need an extraordinary delay */

	delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
@@ -887,7 +885,7 @@ int xhci_suspend(struct xhci_hcd *xhci) 
	/* step 4: set CSS flag */

	command = readl(&xhci->op_regs->command);

	command |= CMD_CSS;

	xhci_writel(xhci, command, &xhci->op_regs->command);

	writel(command, &xhci->op_regs->command);

	if (xhci_handshake(xhci, &xhci->op_regs->status,

				STS_SAVE, 0, 10 * 1000)) {

		xhci_warn(xhci, "WARN: xHC save state timeout\n");
@@ -953,7 +951,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) 
		/* step 3: set CRS flag */

		command = readl(&xhci->op_regs->command);

		command |= CMD_CRS;

		xhci_writel(xhci, command, &xhci->op_regs->command);

		writel(command, &xhci->op_regs->command);

		if (xhci_handshake(xhci, &xhci->op_regs->status,

			      STS_RESTORE, 0, 10 * 1000)) {

			xhci_warn(xhci, "WARN: xHC restore state timeout\n");
@@ -985,10 +983,9 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) 


		xhci_dbg(xhci, "// Disabling event ring interrupts\n");

		temp = readl(&xhci->op_regs->status);

		xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);

		writel(temp & ~STS_EINT, &xhci->op_regs->status);

		temp = readl(&xhci->ir_set->irq_pending);

		xhci_writel(xhci, ER_IRQ_DISABLE(temp),

				&xhci->ir_set->irq_pending);

		writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);

		xhci_print_ir_set(xhci, 0);



		xhci_dbg(xhci, "cleaning up memory\n");
@@ -1025,7 +1022,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) 
	/* step 4: set Run/Stop bit */

	command = readl(&xhci->op_regs->command);

	command |= CMD_RUN;

	xhci_writel(xhci, command, &xhci->op_regs->command);

	writel(command, &xhci->op_regs->command);

	xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,

		  0, 250 * 1000);
@@ -4082,7 +4079,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 
			spin_lock_irqsave(&xhci->lock, flags);



			hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);

			xhci_writel(xhci, hlpm_val, hlpm_addr);

			writel(hlpm_val, hlpm_addr);

			/* flush write */

			readl(hlpm_addr);

		} else {
@@ -4091,15 +4088,15 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 


		pm_val &= ~PORT_HIRD_MASK;

		pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);

		xhci_writel(xhci, pm_val, pm_addr);

		writel(pm_val, pm_addr);

		pm_val = readl(pm_addr);

		pm_val |= PORT_HLE;

		xhci_writel(xhci, pm_val, pm_addr);

		writel(pm_val, pm_addr);

		/* flush write */

		readl(pm_addr);

	} else {

		pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);

		xhci_writel(xhci, pm_val, pm_addr);

		writel(pm_val, pm_addr);

		/* flush write */

		readl(pm_addr);

		if (udev->usb2_hw_lpm_besl_capable) {

drivers/usb/host/xhci.h

+0 −8
Original line number Diff line number Diff line
@@ -1595,14 +1595,6 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 
#define xhci_warn_ratelimited(xhci, fmt, args...) \

	dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)



/* TODO: copied from ehci.h - can be refactored? */

/* xHCI spec says all registers are little endian */

static inline void xhci_writel(struct xhci_hcd *xhci,

		const unsigned int val, __le32 __iomem *regs)

{

	writel(val, regs);

}



/*

 * Registers should always be accessed with double word or quad word accesses.

 *