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Commit 20253de9 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge branch 'upstream-greg' of... 

Merge branch 'upstream-greg' of gregkh@master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
parents b7277155 357eb4cf

arch/ppc/platforms/85xx/mpc8560_ads.c

+89 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <linux/initrd.h>

#include <linux/module.h>

#include <linux/fsl_devices.h>

#include <linux/fs_enet_pd.h>



#include <asm/system.h>

#include <asm/pgtable.h>
@@ -58,6 +59,71 @@ 
 * Setup the architecture

 *

 */

static void init_fcc_ioports(void)

{

	struct immap *immap;

	struct io_port *io;

	u32 tempval;



	immap = cpm2_immr;



	io = &immap->im_ioport;

	/* FCC2/3 are on the ports B/C. */

	tempval = in_be32(&io->iop_pdirb);

	tempval &= ~PB2_DIRB0;

	tempval |= PB2_DIRB1;

	out_be32(&io->iop_pdirb, tempval);



	tempval = in_be32(&io->iop_psorb);

	tempval &= ~PB2_PSORB0;

	tempval |= PB2_PSORB1;

	out_be32(&io->iop_psorb, tempval);



	tempval = in_be32(&io->iop_pparb);

	tempval |= (PB2_DIRB0 | PB2_DIRB1);

	out_be32(&io->iop_pparb, tempval);



	tempval = in_be32(&io->iop_pdirb);

	tempval &= ~PB3_DIRB0;

	tempval |= PB3_DIRB1;

	out_be32(&io->iop_pdirb, tempval);



	tempval = in_be32(&io->iop_psorb);

	tempval &= ~PB3_PSORB0;

	tempval |= PB3_PSORB1;

	out_be32(&io->iop_psorb, tempval);



	tempval = in_be32(&io->iop_pparb);

	tempval |= (PB3_DIRB0 | PB3_DIRB1);

	out_be32(&io->iop_pparb, tempval);



        tempval = in_be32(&io->iop_pdirc);

        tempval |= PC3_DIRC1;

        out_be32(&io->iop_pdirc, tempval);



        tempval = in_be32(&io->iop_pparc);

        tempval |= PC3_DIRC1;

        out_be32(&io->iop_pparc, tempval);



	/* Port C has clocks......  */

	tempval = in_be32(&io->iop_psorc);

	tempval &= ~(CLK_TRX);

	out_be32(&io->iop_psorc, tempval);



	tempval = in_be32(&io->iop_pdirc);

	tempval &= ~(CLK_TRX);

	out_be32(&io->iop_pdirc, tempval);

	tempval = in_be32(&io->iop_pparc);

	tempval |= (CLK_TRX);

	out_be32(&io->iop_pparc, tempval);



	/* Configure Serial Interface clock routing.

	 * First,  clear all FCC bits to zero,

	 * then set the ones we want.

	 */

	immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);

	immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;

}



static void __init

mpc8560ads_setup_arch(void)
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void) 
	unsigned int freq;

	struct gianfar_platform_data *pdata;

	struct gianfar_mdio_data *mdata;

	struct fs_platform_info *fpi;



	cpm2_reset();
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void) 
		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);

	}



	init_fcc_ioports();

	ppc_sys_device_remove(MPC85xx_CPM_FCC1);



	fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);

	if (fpi) {

		memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);

		fpi->bus_id = "0:02";

		fpi->phy_addr = 2;

		fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;

		fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];

	}



	fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);

	if (fpi) {

		memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);

		fpi->macaddr[5] += 1;

		fpi->bus_id = "0:03";

		fpi->phy_addr = 3;

		fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;

		fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];

	}



#ifdef CONFIG_BLK_DEV_INITRD

	if (initrd_start)

		ROOT_DEV = Root_RAM0;

arch/ppc/platforms/85xx/mpc85xx_ads_common.h

+19 −0
Original line number Diff line number Diff line
@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init; 


#define MPC85XX_PCI1_IO_SIZE	0x01000000



/* FCC1 Clock Source Configuration.  These can be

 * redefined in the board specific file.

 *    Can only choose from CLK9-12 */

#define F1_RXCLK       12

#define F1_TXCLK       11



/* FCC2 Clock Source Configuration.  These can be

 * redefined in the board specific file.

 *    Can only choose from CLK13-16 */

#define F2_RXCLK       13

#define F2_TXCLK       14



/* FCC3 Clock Source Configuration.  These can be

 * redefined in the board specific file.

 *    Can only choose from CLK13-16 */

#define F3_RXCLK       15

#define F3_TXCLK       16





#endif				/* __MACH_MPC85XX_ADS_H__ */

arch/ppc/platforms/mpc8272ads_setup.c

+85 −69
Original line number Diff line number Diff line
@@ -56,43 +56,34 @@ static struct fs_uart_platform_info mpc8272_uart_pdata[] = { 
	},

};



static struct fs_mii_bus_info mii_bus_info = {

	.method                 = fsmii_bitbang,

	.id                     = 0,

	.i.bitbang = {

		.mdio_port	= fsiop_portc,

		.mdio_bit	= 18,

		.mdc_port	= fsiop_portc,

		.mdc_bit	= 19,

static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {

	.mdio_dat.bit	= 18,

	.mdio_dir.bit	= 18,

	.mdc_dat.bit	= 19,

	.delay		= 1,

	},

};



static struct fs_platform_info mpc82xx_fcc1_pdata = {

static struct fs_platform_info mpc82xx_enet_pdata[] = {

	[fsid_fcc1] = {

		.fs_no		= fsid_fcc1,

		.cp_page	= CPM_CR_FCC1_PAGE,

		.cp_block 	= CPM_CR_FCC1_SBLOCK,



		.clk_trx 	= (PC_F1RXCLK | PC_F1TXCLK),

		.clk_route	= CMX1_CLK_ROUTE,

		.clk_mask	= CMX1_CLK_MASK,

		.init_ioports 	= init_fcc1_ioports,



	.phy_addr	= 0,

#ifdef PHY_INTERRUPT

	.phy_irq	= PHY_INTERRUPT,

#else

	.phy_irq	= -1;

#endif

		.mem_offset	= FCC1_MEM_OFFSET,

	.bus_info	= &mii_bus_info,



		.rx_ring	= 32,

		.tx_ring	= 32,

		.rx_copybreak	= 240,

		.use_napi	= 0,

		.napi_weight	= 17,

};



static struct fs_platform_info mpc82xx_fcc2_pdata = {

		.bus_id		= "0:00",

	},

	[fsid_fcc2] = {

		.fs_no		= fsid_fcc2,

		.cp_page	= CPM_CR_FCC2_PAGE,

		.cp_block 	= CPM_CR_FCC2_SBLOCK,
@@ -101,19 +92,15 @@ static struct fs_platform_info mpc82xx_fcc2_pdata = { 
		.clk_mask	= CMX2_CLK_MASK,

		.init_ioports	= init_fcc2_ioports,



	.phy_addr	= 3,

#ifdef PHY_INTERRUPT

	.phy_irq	= PHY_INTERRUPT,

#else

	.phy_irq	= -1;

#endif

		.mem_offset	= FCC2_MEM_OFFSET,

	.bus_info	= &mii_bus_info,



		.rx_ring	= 32,

		.tx_ring	= 32,

		.rx_copybreak	= 240,

		.use_napi	= 0,

		.napi_weight	= 17,

		.bus_id		= "0:03",

	},

};



static void init_fcc1_ioports(void)
@@ -209,20 +196,21 @@ static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, 
	bd_t* bi = (void*)__res;

	int fs_no = fsid_fcc1+pdev->id-1;



	mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;

	mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;



	switch(fs_no) {

		case fsid_fcc1:

			memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);

			pdev->dev.platform_data = &mpc82xx_fcc1_pdata;

		break;

		case fsid_fcc2:

			memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);

			mpc82xx_fcc2_pdata.macaddr[5] ^= 1;

			pdev->dev.platform_data = &mpc82xx_fcc2_pdata;

		break;

	if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {

		return;

	}



	mpc82xx_enet_pdata[fs_no].dpram_offset=

			(u32)cpm2_immr->im_dprambase;

	mpc82xx_enet_pdata[fs_no].fcc_regs_c =

			(u32)cpm2_immr->im_fcc_c;

	memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);



	/* prevent dup mac */

	if(fs_no == fsid_fcc2)

		mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;



	pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];

}



static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
@@ -274,6 +262,29 @@ static void init_scc4_uart_ioports(void) 
	iounmap(immap);

}



static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,

					      int idx)

{

	m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;

	m82xx_mii_bb_pdata.irq[1] = -1;

	m82xx_mii_bb_pdata.irq[2] = -1;

	m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;

	m82xx_mii_bb_pdata.irq[31] = -1;





	m82xx_mii_bb_pdata.mdio_dat.offset =

				(u32)&cpm2_immr->im_ioport.iop_pdatc;



	m82xx_mii_bb_pdata.mdio_dir.offset =

				(u32)&cpm2_immr->im_ioport.iop_pdirc;



	m82xx_mii_bb_pdata.mdc_dat.offset =

				(u32)&cpm2_immr->im_ioport.iop_pdatc;





	pdev->dev.platform_data = &m82xx_mii_bb_pdata;

}



static int mpc8272ads_platform_notify(struct device *dev)

{

	static const struct platform_notify_dev_map dev_map[] = {
@@ -285,6 +296,10 @@ static int mpc8272ads_platform_notify(struct device *dev) 
			.bus_id = "fsl-cpm-scc:uart",

			.rtn = mpc8272ads_fixup_uart_pdata,

		},

		{

			.bus_id = "fsl-bb-mdio",

			.rtn = mpc8272ads_fixup_mdio_pdata,

		},

		{

			.bus_id = NULL

		}
@@ -319,6 +334,7 @@ int __init mpc8272ads_init(void) 
	ppc_sys_device_enable(MPC82xx_CPM_SCC4);

#endif



	ppc_sys_device_enable(MPC82xx_MDIO_BB);



	return 0;

}

arch/ppc/platforms/mpc866ads_setup.c

+96 −96
Original line number Diff line number Diff line 
/*arch/ppc/platforms/mpc885ads-setup.c

/*arch/ppc/platforms/mpc866ads-setup.c

 *

 * Platform setup for the Freescale mpc885ads board

 * Platform setup for the Freescale mpc866ads board

 *

 * Vitaly Bordug <vbordug@ru.mvista.com>

 *

 * Copyright 2005 MontaVista Software Inc.

 * Copyright 2005-2006 MontaVista Software Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2. This program is licensed "as is" without any warranty of any
@@ -42,20 +42,12 @@ static void setup_scc1_ioports(void); 
static void setup_smc1_ioports(void);

static void setup_smc2_ioports(void);



static struct fs_mii_bus_info fec_mii_bus_info = {

	.method = fsmii_fec,

	.id = 0,

};

static struct fs_mii_fec_platform_info	mpc8xx_mdio_fec_pdata;



static struct fs_mii_bus_info scc_mii_bus_info = {

	.method = fsmii_fixed,

	.id = 0,

	.i.fixed.speed = 10,

	.i.fixed.duplex = 0,

};

static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;



static struct fs_platform_info mpc8xx_fec_pdata[] = {

	{

static struct fs_platform_info mpc8xx_enet_pdata[] = {

	[fsid_fec1] = {

		.rx_ring = 128,

		.tx_ring = 16,

		.rx_copybreak = 240,
@@ -63,28 +55,23 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { 
		.use_napi = 1,

		.napi_weight = 17,



	 .phy_addr = 15,

	 .phy_irq = -1,



	 .use_rmii = 0,



	 .bus_info = &fec_mii_bus_info,

	 }

};

		.init_ioports = setup_fec1_ioports,



static struct fs_platform_info mpc8xx_scc_pdata = {

		.bus_id = "0:0f",

		.has_phy = 1,

	},

	[fsid_scc1] = {

		.rx_ring = 64,

		.tx_ring = 8,

		.rx_copybreak = 240,



		.use_napi = 1,

		.napi_weight = 17,



	.phy_addr = -1,

	.phy_irq = -1,



	.bus_info = &scc_mii_bus_info,

		.init_ioports = setup_scc1_ioports,



		.bus_id = "fixed@100:1",

	},

};



static struct fs_uart_platform_info mpc866_uart_pdata[] = {
@@ -207,63 +194,6 @@ static void setup_scc1_ioports(void) 


}



static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)

{

	struct fs_platform_info *fpi = pdev->dev.platform_data;



	volatile cpm8xx_t *cp;

	bd_t *bd = (bd_t *) __res;

	char *e;

	int i;



	/* Get pointer to Communication Processor */

	cp = cpmp;

	switch (fs_no) {

	case fsid_fec1:

		fpi = &mpc8xx_fec_pdata[0];

		fpi->init_ioports = &setup_fec1_ioports;



		break;

	case fsid_scc1:

		fpi = &mpc8xx_scc_pdata;

		fpi->init_ioports = &setup_scc1_ioports;



		break;

	default:

		printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);

		return;

	}



	pdev->dev.platform_data = fpi;

	fpi->fs_no = fs_no;



	e = (unsigned char *)&bd->bi_enetaddr;

	for (i = 0; i < 6; i++)

		fpi->macaddr[i] = *e++;



	fpi->macaddr[5 - pdev->id]++;



}



static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,

					   int idx)

{

	/* This is for FEC devices only */

	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))

		return;

	mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);

}



static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,

					   int idx)

{

	/* This is for SCC devices only */

	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))

		return;



	mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);

}



static void setup_smc1_ioports(void)

{

	immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -315,6 +245,56 @@ static void setup_smc2_ioports(void) 


}



static int ma_count = 0;



static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)

{

	struct fs_platform_info *fpi;



	volatile cpm8xx_t *cp;

	bd_t *bd = (bd_t *) __res;

	char *e;

	int i;



	/* Get pointer to Communication Processor */

	cp = cpmp;



	if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {

		printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);

		return;

	}





	fpi = &mpc8xx_enet_pdata[fs_no];

	fpi->fs_no = fs_no;

	pdev->dev.platform_data = fpi;



	e = (unsigned char *)&bd->bi_enetaddr;

	for (i = 0; i < 6; i++)

		fpi->macaddr[i] = *e++;



	fpi->macaddr[5] += ma_count++;

}



static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,

					   int idx)

{

	/* This is for FEC devices only */

	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))

		return;

	mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);

}



static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,

					   int idx)

{

	/* This is for SCC devices only */

	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))

		return;



	mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);

}



static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,

                                              int idx)

{
@@ -359,6 +339,9 @@ static int mpc866ads_platform_notify(struct device *dev) 


int __init mpc866ads_init(void)

{

	bd_t *bd = (bd_t *) __res;

	struct fs_mii_fec_platform_info* fmpi;



	printk(KERN_NOTICE "mpc866ads: Init\n");



	platform_notify = mpc866ads_platform_notify;
@@ -366,11 +349,20 @@ int __init mpc866ads_init(void) 
	ppc_sys_device_initfunc();

	ppc_sys_device_disable_all();



#ifdef MPC8xx_SECOND_ETH_SCC1

#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1

	ppc_sys_device_enable(MPC8xx_CPM_SCC1);

#endif

	ppc_sys_device_enable(MPC8xx_CPM_FEC1);



	ppc_sys_device_enable(MPC8xx_MDIO_FEC);



	fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =

		&mpc8xx_mdio_fec_pdata;



	fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;

	/* No PHY interrupt line here */

	fmpi->irq[0xf] = -1;



/* Since either of the uarts could be used as console, they need to ready */

#ifdef CONFIG_SERIAL_CPM_SMC1

	ppc_sys_device_enable(MPC8xx_CPM_SMC1);
@@ -381,6 +373,14 @@ int __init mpc866ads_init(void) 
	ppc_sys_device_enable(MPC8xx_CPM_SMC2);

	ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);

#endif

	ppc_sys_device_enable(MPC8xx_MDIO_FEC);



	fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =

		&mpc8xx_mdio_fec_pdata;



	fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;

	/* No PHY interrupt line here */

	fmpi->irq[0xf] = -1;



	return 0;

}

arch/ppc/platforms/mpc885ads_setup.c

+66 −109
Original line number Diff line number Diff line
@@ -38,7 +38,10 @@ extern unsigned char __res[]; 
static void setup_smc1_ioports(void);

static void setup_smc2_ioports(void);



static void __init mpc885ads_scc_phy_init(char);

static struct fs_mii_fec_platform_info	mpc8xx_mdio_fec_pdata;

static void setup_fec1_ioports(void);

static void setup_fec2_ioports(void);

static void setup_scc3_ioports(void);



static struct fs_uart_platform_info mpc885_uart_pdata[] = {

	[fsid_smc1_uart] = {
@@ -61,23 +64,8 @@ static struct fs_uart_platform_info mpc885_uart_pdata[] = { 
 	},

};



static struct fs_mii_bus_info fec_mii_bus_info = {

	.method = fsmii_fec,

	.id = 0,

};



static struct fs_mii_bus_info scc_mii_bus_info = {

#ifdef CONFIG_SCC_ENET_8xx_FIXED

	.method = fsmii_fixed,

#else

	.method = fsmii_fec,

#endif



	.id = 0,

};



static struct fs_platform_info mpc8xx_fec_pdata[] = {

	{

static struct fs_platform_info mpc8xx_enet_pdata[] = {

	[fsid_fec1] = {

	 .rx_ring = 128,

	 .tx_ring = 16,

	 .rx_copybreak = 240,
@@ -85,11 +73,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { 
	 .use_napi = 1,

	 .napi_weight = 17,



	 .phy_addr = 0,

	 .phy_irq = SIU_IRQ7,

	 .init_ioports = setup_fec1_ioports,



	 .bus_info = &fec_mii_bus_info,

	 }, {

          .bus_id = "0:00",

          .has_phy = 1,

	 },

	[fsid_fec2] = {

	     .rx_ring = 128,

	     .tx_ring = 16,

	     .rx_copybreak = 240,
@@ -97,14 +86,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { 
	     .use_napi = 1,

	     .napi_weight = 17,



	     .phy_addr = 1,

	     .phy_irq = SIU_IRQ7,



	     .bus_info = &fec_mii_bus_info,

	     }

};

	     .init_ioports = setup_fec2_ioports,



static struct fs_platform_info mpc8xx_scc_pdata = {

 	     .bus_id = "0:01",

 	     .has_phy = 1,

	     },

	[fsid_scc3] = {

		.rx_ring = 64,

		.tx_ring = 8,

		.rx_copybreak = 240,
@@ -112,19 +99,18 @@ static struct fs_platform_info mpc8xx_scc_pdata = { 
		.use_napi = 1,

		.napi_weight = 17,



	.phy_addr = 2,

#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED

	.phy_irq = -1,

		.init_ioports = setup_scc3_ioports,

#ifdef CONFIG_FIXED_MII_10_FDX

		.bus_id = "fixed@100:1",

#else

	.phy_irq = SIU_IRQ7,

		.bus_id = "0:02",

 #endif



	.bus_info = &scc_mii_bus_info,

	},

};



void __init board_init(void)

{

	volatile cpm8xx_t *cp = cpmp;

	cpm8xx_t *cp = cpmp;

 	unsigned int *bcsr_io;



#ifdef CONFIG_FS_ENET
@@ -164,6 +150,14 @@ void __init board_init(void) 
	/* use MDC for MII (common) */

	setbits16(&immap->im_ioport.iop_pdpar, 0x0080);

	clrbits16(&immap->im_ioport.iop_pddir, 0x0080);

	bcsr_io = ioremap(BCSR5, sizeof(unsigned long));

	clrbits32(bcsr_io,BCSR5_MII1_EN);

	clrbits32(bcsr_io,BCSR5_MII1_RST);

#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2

	clrbits32(bcsr_io,BCSR5_MII2_EN);

	clrbits32(bcsr_io,BCSR5_MII2_RST);

#endif

	iounmap(bcsr_io);

#endif

}
@@ -194,8 +188,8 @@ static void setup_fec2_ioports(void) 
	/* configure FEC2 pins */

	setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);

	setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);

	setbits32(&immap->im_cpm.cp_peso, 0x00037800);

	clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);

	setbits32(&immap->im_cpm.cp_peso, 0x00037800);

	clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);

}
@@ -213,6 +207,8 @@ static void setup_scc3_ioports(void) 


	/* Enable the PHY.

	 */

	clrbits32(bcsr_io+4, BCSR4_ETH10_RST);

	udelay(1000);

	setbits32(bcsr_io+4, BCSR4_ETH10_RST);

	/* Configure port A pins for Txd and Rxd.

	 */
@@ -254,34 +250,35 @@ static void setup_scc3_ioports(void) 
	clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);

	setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);



	setbits32(bcsr_io+1, BCSR1_ETHEN);

	setbits32(bcsr_io+4, BCSR1_ETHEN);

	iounmap(bcsr_io);

}



static int mac_count = 0;



static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)

{

	struct fs_platform_info *fpi = pdev->dev.platform_data;



	volatile cpm8xx_t *cp;

 	struct fs_platform_info *fpi;

	bd_t *bd = (bd_t *) __res;

	char *e;

	int i;



	/* Get pointer to Communication Processor */

	cp = cpmp;

	if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {

		printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);

		return;

	}



	fpi = &mpc8xx_enet_pdata[fs_no];



	switch (fs_no) {

	case fsid_fec1:

		fpi = &mpc8xx_fec_pdata[0];

		fpi->init_ioports = &setup_fec1_ioports;

		break;

	case fsid_fec2:

		fpi = &mpc8xx_fec_pdata[1];

		fpi->init_ioports = &setup_fec2_ioports;

		break;

	case fsid_scc3:

		fpi = &mpc8xx_scc_pdata;

		fpi->init_ioports = &setup_scc3_ioports;

		mpc885ads_scc_phy_init(fpi->phy_addr);

		break;

	default:

    	        printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
@@ -295,7 +292,7 @@ static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) 
	for (i = 0; i < 6; i++)

		fpi->macaddr[i] = *e++;



	fpi->macaddr[5 - pdev->id]++;

	fpi->macaddr[5] += mac_count++;



}
@@ -318,58 +315,6 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, 
	mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);

}



/* SCC ethernet controller does not have MII management channel. FEC1 MII

 * channel is used to communicate with the 10Mbit PHY.

 */



#define MII_ECNTRL_PINMUX        0x4

#define FEC_ECNTRL_PINMUX        0x00000004

#define FEC_RCNTRL_MII_MODE        0x00000004



/* Make MII read/write commands.

 */

#define mk_mii_write(REG, VAL, PHY_ADDR)    (0x50020000 | (((REG) & 0x1f) << 18) | \

                ((VAL) & 0xffff) | ((PHY_ADDR) << 23))



static void mpc885ads_scc_phy_init(char phy_addr)

{

	volatile immap_t *immap;

	volatile fec_t *fecp;

	bd_t *bd;



	bd = (bd_t *) __res;

	immap = (immap_t *) IMAP_ADDR;	/* pointer to internal registers */

	fecp = &(immap->im_cpm.cp_fec);



	/* Enable MII pins of the FEC1

	 */

	setbits16(&immap->im_ioport.iop_pdpar, 0x0080);

	clrbits16(&immap->im_ioport.iop_pddir, 0x0080);

	/* Set MII speed to 2.5 MHz

	 */

	out_be32(&fecp->fec_mii_speed,

		 ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);



	/* Enable FEC pin MUX

	 */

	setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);

	setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);



	out_be32(&fecp->fec_mii_data,

		 mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));

	udelay(100);

	out_be32(&fecp->fec_mii_data,

		 mk_mii_write(MII_ADVERTISE,

			      ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));

	udelay(100);



	/* Disable FEC MII settings

	 */

	clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);

	clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);

	out_be32(&fecp->fec_mii_speed, 0);

}



static void setup_smc1_ioports(void)

{

        immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -462,6 +407,9 @@ static int mpc885ads_platform_notify(struct device *dev) 


int __init mpc885ads_init(void)

{

	struct fs_mii_fec_platform_info* fmpi;

	bd_t *bd = (bd_t *) __res;



	printk(KERN_NOTICE "mpc885ads: Init\n");



	platform_notify = mpc885ads_platform_notify;
@@ -471,8 +419,17 @@ int __init mpc885ads_init(void) 


	ppc_sys_device_enable(MPC8xx_CPM_FEC1);



	ppc_sys_device_enable(MPC8xx_MDIO_FEC);

	fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =

		&mpc8xx_mdio_fec_pdata;



	fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;



	/* No PHY interrupt line here */

	fmpi->irq[0xf] = SIU_IRQ7;



#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3

	ppc_sys_device_enable(MPC8xx_CPM_SCC1);

	ppc_sys_device_enable(MPC8xx_CPM_SCC3);



#endif

#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2