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Commit 1faf8692 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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clk: renesas: cpg-mssr: Document r8a7796 support 



Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarRob Herring <robh@kernel.org>
Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 1a695a90

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+4 −3
Original line number Diff line number Diff line
@@ -13,7 +13,8 @@ They provide the following functionalities: 


Required Properties:

  - compatible: Must be one of:

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)



  - reg: Base address and length of the memory resource used by the CPG/MSSR

    block
@@ -21,8 +22,8 @@ Required Properties: 
  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r8a7795)

      - "extalr" (r8a7795)

      - "extal" (r8a7795, r8a7796)

      - "extalr" (r8a7795, r8a7796)



  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"