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Commit 1f934641 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/irq: Remove sis apic bug workaround 



The SiS apic bug workaround is now obsolete as we cache the register
values for performance reasons.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarJiang Liu <jiang.liu@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: David Cohen <david.a.cohen@linux.intel.com>
Cc: Sander Eikelenboom <linux@eikelenboom.it>
Cc: David Vrabel <david.vrabel@citrix.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dimitri Sivanich <sivanich@sgi.com>
Cc: Grant Likely <grant.likely@linaro.org>
Link: http://lkml.kernel.org/r/1428978610-28986-22-git-send-email-jiang.liu@linux.intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 0be275e3

arch/x86/include/asm/io_apic.h

+0 −3
Original line number Diff line number Diff line
@@ -120,9 +120,6 @@ extern int mp_irq_entries; 
/* MP IRQ source entries */

extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];



/* Older SiS APIC requires we rewrite the index register */

extern int sis_apic_bug;



/* 1 if "noapic" boot option passed */

extern int skip_ioapic_setup;

arch/x86/kernel/apic/io_apic.c

+10 −25
Original line number Diff line number Diff line
@@ -18,6 +18,16 @@ 
 *					and Rolf G. Tews

 *					for testing these extensively

 *	Paul Diefenbaugh	:	Added full ACPI support

 *

 * Historical information which is worth to be preserved:

 *

 * - SiS APIC rmw bug:

 *

 *	We used to have a workaround for a bug in SiS chips which

 *	required to rewrite the index register for a read-modify-write

 *	operation as the chip lost the index information which was

 *	setup for the read already. We cache the data now, so that

 *	workaround has been removed.

 */



#include <linux/mm.h>
@@ -66,17 +76,6 @@ 
#define for_each_irq_pin(entry, head) \

	list_for_each_entry(entry, &head, list)



/*

 * Is the SiS APIC rmw bug present ?

 *      -1 = don't know, 0 = no, 1 = yes

 * When doing a read-modify-write operation on IOAPIC registers, older SiS APIC

 * requires we rewrite the index register again where the read already set up

 * the index register.

 * The code to make use of sis_apic_bug has been removed, but we don't want to

 * lose this knowledge.

 */

int sis_apic_bug = -1;



static DEFINE_RAW_SPINLOCK(ioapic_lock);

static DEFINE_MUTEX(ioapic_mutex);

static unsigned int ioapic_dynirq_base;
@@ -2320,20 +2319,6 @@ void __init setup_IO_APIC(void) 
	ioapic_initialized = 1;

}



/*

 *      Called after all the initialization is done. If we didn't find any

 *      APIC bugs then we can allow the modify fast path

 */



static int __init io_apic_bug_finalize(void)

{

	if (sis_apic_bug == -1)

		sis_apic_bug = 0;

	return 0;

}



late_initcall(io_apic_bug_finalize);



static void resume_ioapic_id(int ioapic_idx)

{

	unsigned long flags;

drivers/pci/quirks.c

+0 −7
Original line number Diff line number Diff line
@@ -819,13 +819,6 @@ static void quirk_amd_ioapic(struct pci_dev *dev) 
	}

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);



static void quirk_ioapic_rmw(struct pci_dev *dev)

{

	if (dev->devfn == 0 && dev->bus->number == 0)

		sis_apic_bug = 1;

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_ANY_ID,			quirk_ioapic_rmw);

#endif /* CONFIG_X86_IO_APIC */



/*