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Commit 1f5826bd authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle
Browse files

[MIPS] Added missing cases for rdhwr emulation 



Some of these are architecturally required for R2 processors so lets try
to be bit closer to the real thing.  This also provides access to the
CPU cycle timer, even on multiprocessors.  In that aspect its currently
bug compatible to what would happen on a R2-based SMP.

Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 0ec734c2

arch/mips/kernel/traps.c

+25 −6
Original line number Diff line number Diff line
@@ -534,8 +534,7 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 


/*

 * Simulate trapping 'rdhwr' instructions to provide user accessible

 * registers not implemented in hardware.  The only current use of this

 * is the thread area pointer.

 * registers not implemented in hardware.

 */

static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)

{
@@ -545,6 +544,26 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 
		int rd = (opcode & RD) >> 11;

		int rt = (opcode & RT) >> 16;

		switch (rd) {

		case 0:		/* CPU number */

			regs->regs[rt] = smp_processor_id();

			return 0;

		case 1:		/* SYNCI length */

			regs->regs[rt] = min(current_cpu_data.dcache.linesz,

					     current_cpu_data.icache.linesz);

			return 0;

		case 2:		/* Read count register */

			regs->regs[rt] = read_c0_count();

			return 0;

		case 3:		/* Count register resolution */

			switch (current_cpu_data.cputype) {

			case CPU_20KC:

			case CPU_25KF:

				regs->regs[rt] = 1;

				break;

			default:

				regs->regs[rt] = 2;

			}

			return 0;

		case 29:

			regs->regs[rt] = ti->tp_value;

			return 0;