Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable (1e87347c) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/mach-dove/common.c

+32 −584

Original line number	Diff line number	Diff line
		@@ -16,10 +16,8 @@
		#include <linux/serial_8250.h>
		#include <linux/clk.h>
		#include <linux/mbus.h>
		#include <linux/mv643xx_eth.h>
		#include <linux/mv643xx_i2c.h>
		#include <linux/ata_platform.h>
		#include <linux/spi/orion_spi.h>
		#include <linux/serial_8250.h>
		#include <linux/gpio.h>
		#include <asm/page.h>
		#include <asm/setup.h>
		@@ -32,11 +30,12 @@
		#include <mach/bridge-regs.h>
		#include <asm/mach/arch.h>
		#include <linux/irq.h>
		#include <plat/mv_xor.h>
		#include <plat/ehci-orion.h>
		#include <plat/time.h>
		#include <plat/common.h>
		#include "common.h"

		static int get_tclk(void);

		/*****************************************************************************
		* I/O Address Mapping
		****************************************************************************/
		@@ -69,464 +68,107 @@ void __init dove_map_io(void)
		iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
		}

		/*****************************************************************************
		* EHCI
		****************************************************************************/
		static struct orion_ehci_data dove_ehci_data = {
		.dram = &dove_mbus_dram_info,
		.phy_version = EHCI_PHY_NA,
		};

		static u64 ehci_dmamask = DMA_BIT_MASK(32);

		/*****************************************************************************
		* EHCI0
		****************************************************************************/
		static struct resource dove_ehci0_resources[] = {
		{
		.start = DOVE_USB0_PHYS_BASE,
		.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_USB0,
		.end = IRQ_DOVE_USB0,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_ehci0 = {
		.name = "orion-ehci",
		.id = 0,
		.dev = {
		.dma_mask = &ehci_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data = &dove_ehci_data,
		},
		.resource = dove_ehci0_resources,
		.num_resources = ARRAY_SIZE(dove_ehci0_resources),
		};

		void __init dove_ehci0_init(void)
		{
		platform_device_register(&dove_ehci0);
		orion_ehci_init(&dove_mbus_dram_info,
		DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
		}

		/*****************************************************************************
		* EHCI1
		****************************************************************************/
		static struct resource dove_ehci1_resources[] = {
		{
		.start = DOVE_USB1_PHYS_BASE,
		.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_USB1,
		.end = IRQ_DOVE_USB1,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_ehci1 = {
		.name = "orion-ehci",
		.id = 1,
		.dev = {
		.dma_mask = &ehci_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data = &dove_ehci_data,
		},
		.resource = dove_ehci1_resources,
		.num_resources = ARRAY_SIZE(dove_ehci1_resources),
		};

		void __init dove_ehci1_init(void)
		{
		platform_device_register(&dove_ehci1);
		orion_ehci_1_init(&dove_mbus_dram_info,
		DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
		}

		/*****************************************************************************
		* GE00
		****************************************************************************/
		struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
		.t_clk = 0,
		.dram = &dove_mbus_dram_info,
		};

		static struct resource dove_ge00_shared_resources[] = {
		{
		.name = "ge00 base",
		.start = DOVE_GE00_PHYS_BASE + 0x2000,
		.end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
		},
		};

		static struct platform_device dove_ge00_shared = {
		.name = MV643XX_ETH_SHARED_NAME,
		.id = 0,
		.dev = {
		.platform_data = &dove_ge00_shared_data,
		},
		.num_resources = 1,
		.resource = dove_ge00_shared_resources,
		};

		static struct resource dove_ge00_resources[] = {
		{
		.name = "ge00 irq",
		.start = IRQ_DOVE_GE00_SUM,
		.end = IRQ_DOVE_GE00_SUM,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_ge00 = {
		.name = MV643XX_ETH_NAME,
		.id = 0,
		.num_resources = 1,
		.resource = dove_ge00_resources,
		.dev = {
		.coherent_dma_mask = 0xffffffff,
		},
		};

		void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
		{
		eth_data->shared = &dove_ge00_shared;
		dove_ge00.dev.platform_data = eth_data;

		platform_device_register(&dove_ge00_shared);
		platform_device_register(&dove_ge00);
		orion_ge00_init(eth_data, &dove_mbus_dram_info,
		DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
		0, get_tclk());
		}

		/*****************************************************************************
		* SoC RTC
		****************************************************************************/
		static struct resource dove_rtc_resource[] = {
		{
		.start = DOVE_RTC_PHYS_BASE,
		.end = DOVE_RTC_PHYS_BASE + 32 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_RTC,
		.flags = IORESOURCE_IRQ,
		}
		};

		void __init dove_rtc_init(void)
		{
		platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
		orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
		}

		/*****************************************************************************
		* SATA
		****************************************************************************/
		static struct resource dove_sata_resources[] = {
		{
		.name = "sata base",
		.start = DOVE_SATA_PHYS_BASE,
		.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.name = "sata irq",
		.start = IRQ_DOVE_SATA,
		.end = IRQ_DOVE_SATA,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_sata = {
		.name = "sata_mv",
		.id = 0,
		.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		},
		.num_resources = ARRAY_SIZE(dove_sata_resources),
		.resource = dove_sata_resources,
		};

		void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
		{
		sata_data->dram = &dove_mbus_dram_info;
		dove_sata.dev.platform_data = sata_data;
		platform_device_register(&dove_sata);
		orion_sata_init(sata_data, &dove_mbus_dram_info,
		DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

		}

		/*****************************************************************************
		* UART0
		****************************************************************************/
		static struct plat_serial8250_port dove_uart0_data[] = {
		{
		.mapbase = DOVE_UART0_PHYS_BASE,
		.membase = (char *)DOVE_UART0_VIRT_BASE,
		.irq = IRQ_DOVE_UART_0,
		.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
		.iotype = UPIO_MEM,
		.regshift = 2,
		.uartclk = 0,
		}, {
		},
		};

		static struct resource dove_uart0_resources[] = {
		{
		.start = DOVE_UART0_PHYS_BASE,
		.end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_UART_0,
		.end = IRQ_DOVE_UART_0,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_uart0 = {
		.name = "serial8250",
		.id = 0,
		.dev = {
		.platform_data = dove_uart0_data,
		},
		.resource = dove_uart0_resources,
		.num_resources = ARRAY_SIZE(dove_uart0_resources),
		};

		void __init dove_uart0_init(void)
		{
		platform_device_register(&dove_uart0);
		orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
		IRQ_DOVE_UART_0, get_tclk());
		}

		/*****************************************************************************
		* UART1
		****************************************************************************/
		static struct plat_serial8250_port dove_uart1_data[] = {
		{
		.mapbase = DOVE_UART1_PHYS_BASE,
		.membase = (char *)DOVE_UART1_VIRT_BASE,
		.irq = IRQ_DOVE_UART_1,
		.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
		.iotype = UPIO_MEM,
		.regshift = 2,
		.uartclk = 0,
		}, {
		},
		};

		static struct resource dove_uart1_resources[] = {
		{
		.start = DOVE_UART1_PHYS_BASE,
		.end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_UART_1,
		.end = IRQ_DOVE_UART_1,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_uart1 = {
		.name = "serial8250",
		.id = 1,
		.dev = {
		.platform_data = dove_uart1_data,
		},
		.resource = dove_uart1_resources,
		.num_resources = ARRAY_SIZE(dove_uart1_resources),
		};

		void __init dove_uart1_init(void)
		{
		platform_device_register(&dove_uart1);
		orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
		IRQ_DOVE_UART_1, get_tclk());
		}

		/*****************************************************************************
		* UART2
		****************************************************************************/
		static struct plat_serial8250_port dove_uart2_data[] = {
		{
		.mapbase = DOVE_UART2_PHYS_BASE,
		.membase = (char *)DOVE_UART2_VIRT_BASE,
		.irq = IRQ_DOVE_UART_2,
		.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
		.iotype = UPIO_MEM,
		.regshift = 2,
		.uartclk = 0,
		}, {
		},
		};

		static struct resource dove_uart2_resources[] = {
		{
		.start = DOVE_UART2_PHYS_BASE,
		.end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_UART_2,
		.end = IRQ_DOVE_UART_2,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_uart2 = {
		.name = "serial8250",
		.id = 2,
		.dev = {
		.platform_data = dove_uart2_data,
		},
		.resource = dove_uart2_resources,
		.num_resources = ARRAY_SIZE(dove_uart2_resources),
		};

		void __init dove_uart2_init(void)
		{
		platform_device_register(&dove_uart2);
		orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
		IRQ_DOVE_UART_2, get_tclk());
		}

		/*****************************************************************************
		* UART3
		****************************************************************************/
		static struct plat_serial8250_port dove_uart3_data[] = {
		{
		.mapbase = DOVE_UART3_PHYS_BASE,
		.membase = (char *)DOVE_UART3_VIRT_BASE,
		.irq = IRQ_DOVE_UART_3,
		.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
		.iotype = UPIO_MEM,
		.regshift = 2,
		.uartclk = 0,
		}, {
		},
		};

		static struct resource dove_uart3_resources[] = {
		{
		.start = DOVE_UART3_PHYS_BASE,
		.end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_UART_3,
		.end = IRQ_DOVE_UART_3,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_uart3 = {
		.name = "serial8250",
		.id = 3,
		.dev = {
		.platform_data = dove_uart3_data,
		},
		.resource = dove_uart3_resources,
		.num_resources = ARRAY_SIZE(dove_uart3_resources),
		};

		void __init dove_uart3_init(void)
		{
		platform_device_register(&dove_uart3);
		orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
		IRQ_DOVE_UART_3, get_tclk());
		}

		/*****************************************************************************
		* SPI0
		* SPI
		****************************************************************************/
		static struct orion_spi_info dove_spi0_data = {
		.tclk = 0,
		};

		static struct resource dove_spi0_resources[] = {
		{
		.start = DOVE_SPI0_PHYS_BASE,
		.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_SPI0,
		.end = IRQ_DOVE_SPI0,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_spi0 = {
		.name = "orion_spi",
		.id = 0,
		.resource = dove_spi0_resources,
		.dev = {
		.platform_data = &dove_spi0_data,
		},
		.num_resources = ARRAY_SIZE(dove_spi0_resources),
		};

		void __init dove_spi0_init(void)
		{
		platform_device_register(&dove_spi0);
		orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
		}

		/*****************************************************************************
		* SPI1
		****************************************************************************/
		static struct orion_spi_info dove_spi1_data = {
		.tclk = 0,
		};

		static struct resource dove_spi1_resources[] = {
		{
		.start = DOVE_SPI1_PHYS_BASE,
		.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.start = IRQ_DOVE_SPI1,
		.end = IRQ_DOVE_SPI1,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_spi1 = {
		.name = "orion_spi",
		.id = 1,
		.resource = dove_spi1_resources,
		.dev = {
		.platform_data = &dove_spi1_data,
		},
		.num_resources = ARRAY_SIZE(dove_spi1_resources),
		};

		void __init dove_spi1_init(void)
		{
		platform_device_register(&dove_spi1);
		orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
		}

		/*****************************************************************************
		* I2C
		****************************************************************************/
		static struct mv64xxx_i2c_pdata dove_i2c_data = {
		.freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
		.freq_n = 3,
		.timeout = 1000, /* Default timeout of 1 second */
		};

		static struct resource dove_i2c_resources[] = {
		{
		.name = "i2c base",
		.start = DOVE_I2C_PHYS_BASE,
		.end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
		.flags = IORESOURCE_MEM,
		}, {
		.name = "i2c irq",
		.start = IRQ_DOVE_I2C,
		.end = IRQ_DOVE_I2C,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct platform_device dove_i2c = {
		.name = MV64XXX_I2C_CTLR_NAME,
		.id = 0,
		.num_resources = ARRAY_SIZE(dove_i2c_resources),
		.resource = dove_i2c_resources,
		.dev = {
		.platform_data = &dove_i2c_data,
		},
		};

		void __init dove_i2c_init(void)
		{
		platform_device_register(&dove_i2c);
		orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
		}

		/*****************************************************************************
		@@ -553,209 +195,23 @@ struct sys_timer dove_timer = {
		.init = dove_timer_init,
		};

		/*****************************************************************************
		* XOR
		****************************************************************************/
		static struct mv_xor_platform_shared_data dove_xor_shared_data = {
		.dram = &dove_mbus_dram_info,
		};

		/*****************************************************************************
		* XOR 0
		****************************************************************************/
		static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);

		static struct resource dove_xor0_shared_resources[] = {
		{
		.name = "xor 0 low",
		.start = DOVE_XOR0_PHYS_BASE,
		.end = DOVE_XOR0_PHYS_BASE + 0xff,
		.flags = IORESOURCE_MEM,
		}, {
		.name = "xor 0 high",
		.start = DOVE_XOR0_HIGH_PHYS_BASE,
		.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
		.flags = IORESOURCE_MEM,
		},
		};

		static struct platform_device dove_xor0_shared = {
		.name = MV_XOR_SHARED_NAME,
		.id = 0,
		.dev = {
		.platform_data = &dove_xor_shared_data,
		},
		.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
		.resource = dove_xor0_shared_resources,
		};

		static struct resource dove_xor00_resources[] = {
		[0] = {
		.start = IRQ_DOVE_XOR_00,
		.end = IRQ_DOVE_XOR_00,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct mv_xor_platform_data dove_xor00_data = {
		.shared = &dove_xor0_shared,
		.hw_id = 0,
		.pool_size = PAGE_SIZE,
		};

		static struct platform_device dove_xor00_channel = {
		.name = MV_XOR_NAME,
		.id = 0,
		.num_resources = ARRAY_SIZE(dove_xor00_resources),
		.resource = dove_xor00_resources,
		.dev = {
		.dma_mask = &dove_xor0_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(64),
		.platform_data = &dove_xor00_data,
		},
		};

		static struct resource dove_xor01_resources[] = {
		[0] = {
		.start = IRQ_DOVE_XOR_01,
		.end = IRQ_DOVE_XOR_01,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct mv_xor_platform_data dove_xor01_data = {
		.shared = &dove_xor0_shared,
		.hw_id = 1,
		.pool_size = PAGE_SIZE,
		};

		static struct platform_device dove_xor01_channel = {
		.name = MV_XOR_NAME,
		.id = 1,
		.num_resources = ARRAY_SIZE(dove_xor01_resources),
		.resource = dove_xor01_resources,
		.dev = {
		.dma_mask = &dove_xor0_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(64),
		.platform_data = &dove_xor01_data,
		},
		};

		void __init dove_xor0_init(void)
		{
		platform_device_register(&dove_xor0_shared);

		/*
		* two engines can't do memset simultaneously, this limitation
		* satisfied by removing memset support from one of the engines.
		*/
		dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
		dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
		platform_device_register(&dove_xor00_channel);

		dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
		dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
		dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
		platform_device_register(&dove_xor01_channel);
		orion_xor0_init(&dove_mbus_dram_info,
		DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
		IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
		}

		/*****************************************************************************
		* XOR 1
		****************************************************************************/
		static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);

		static struct resource dove_xor1_shared_resources[] = {
		{
		.name = "xor 0 low",
		.start = DOVE_XOR1_PHYS_BASE,
		.end = DOVE_XOR1_PHYS_BASE + 0xff,
		.flags = IORESOURCE_MEM,
		}, {
		.name = "xor 0 high",
		.start = DOVE_XOR1_HIGH_PHYS_BASE,
		.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
		.flags = IORESOURCE_MEM,
		},
		};

		static struct platform_device dove_xor1_shared = {
		.name = MV_XOR_SHARED_NAME,
		.id = 1,
		.dev = {
		.platform_data = &dove_xor_shared_data,
		},
		.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
		.resource = dove_xor1_shared_resources,
		};

		static struct resource dove_xor10_resources[] = {
		[0] = {
		.start = IRQ_DOVE_XOR_10,
		.end = IRQ_DOVE_XOR_10,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct mv_xor_platform_data dove_xor10_data = {
		.shared = &dove_xor1_shared,
		.hw_id = 0,
		.pool_size = PAGE_SIZE,
		};

		static struct platform_device dove_xor10_channel = {
		.name = MV_XOR_NAME,
		.id = 2,
		.num_resources = ARRAY_SIZE(dove_xor10_resources),
		.resource = dove_xor10_resources,
		.dev = {
		.dma_mask = &dove_xor1_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(64),
		.platform_data = &dove_xor10_data,
		},
		};

		static struct resource dove_xor11_resources[] = {
		[0] = {
		.start = IRQ_DOVE_XOR_11,
		.end = IRQ_DOVE_XOR_11,
		.flags = IORESOURCE_IRQ,
		},
		};

		static struct mv_xor_platform_data dove_xor11_data = {
		.shared = &dove_xor1_shared,
		.hw_id = 1,
		.pool_size = PAGE_SIZE,
		};

		static struct platform_device dove_xor11_channel = {
		.name = MV_XOR_NAME,
		.id = 3,
		.num_resources = ARRAY_SIZE(dove_xor11_resources),
		.resource = dove_xor11_resources,
		.dev = {
		.dma_mask = &dove_xor1_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(64),
		.platform_data = &dove_xor11_data,
		},
		};

		void __init dove_xor1_init(void)
		{
		platform_device_register(&dove_xor1_shared);

		/*
		* two engines can't do memset simultaneously, this limitation
		* satisfied by removing memset support from one of the engines.
		*/
		dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
		dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
		platform_device_register(&dove_xor10_channel);

		dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
		dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
		dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
		platform_device_register(&dove_xor11_channel);
		orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
		IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
		}

		/*****************************************************************************
		@@ -833,14 +289,6 @@ void __init dove_init(void)
		#endif
		dove_setup_cpu_mbus();

		dove_ge00_shared_data.t_clk = tclk;
		dove_uart0_data[0].uartclk = tclk;
		dove_uart1_data[0].uartclk = tclk;
		dove_uart2_data[0].uartclk = tclk;
		dove_uart3_data[0].uartclk = tclk;
		dove_spi0_data.tclk = tclk;
		dove_spi1_data.tclk = tclk;

		/* internal devices that every board has */
		dove_rtc_init();
		dove_xor0_init();

arch/arm/mach-dove/mpp.c

+43 −91

Original line number	Diff line number	Diff line
		@@ -11,24 +11,17 @@
		#include <linux/kernel.h>
		#include <linux/gpio.h>
		#include <linux/io.h>

		#include <plat/mpp.h>
		#include <mach/dove.h>

		#include "mpp.h"

		#define MPP_NR_REGS 4
		#define MPP_CTRL(i) ((i) == 3 ? \
		DOVE_MPP_CTRL4_VIRT_BASE : \
		DOVE_MPP_VIRT_BASE + (i) * 4)
		#define PMU_SIG_REGS 2
		#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)

		struct dove_mpp_grp {
		int start;
		int end;
		};

		static struct dove_mpp_grp dove_mpp_grp[] = {
		/* Map a group to a range of GPIO pins in that group */
		static const struct dove_mpp_grp dove_mpp_grp[] = {
		[MPP_24_39] = {
		.start = 24,
		.end = 39,
		@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
		.end = 45,
		},
		[MPP_46_51] = {
		.start = 40,
		.end = 45,
		.start = 46,
		.end = 51,
		},
		[MPP_58_61] = {
		.start = 58,
		@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
		},
		};

		/* Enable gpio for a range of pins. mode should be a combination of
		GPIO_OUTPUT_OK \| GPIO_INPUT_OK */
		static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
		{
		int i;
		@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
		orion_gpio_set_valid(i, gpio_mode);
		}

		/* Dump all the extra MPP registers. The platform code will dump the
		registers for pins 0-23. */
		static void dove_mpp_dump_regs(void)
		{
		#ifdef DEBUG
		int i;
		pr_debug("PMU_CTRL4_CTRL: %08x\n",
		readl(DOVE_MPP_CTRL4_VIRT_BASE));

		pr_debug("MPP_CTRL regs:");
		for (i = 0; i < MPP_NR_REGS; i++)
		printk(" %08x", readl(MPP_CTRL(i)));
		printk("\n");
		pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
		readl(DOVE_PMU_MPP_GENERAL_CTRL));

		pr_debug("PMU_SIG_CTRL regs:");
		for (i = 0; i < PMU_SIG_REGS; i++)
		printk(" %08x", readl(PMU_SIG_CTRL(i)));
		printk("\n");

		pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
		pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
		#endif
		}

		static void dove_mpp_cfg_nfc(int sel)
		@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
		writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
		}

		static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
		{
		int start = dove_mpp_grp[num].start;
		int end = dove_mpp_grp[num].end;
		int gpio_mode = sel ? GPIO_OUTPUT_OK \| GPIO_INPUT_OK : 0;

		*mpp_ctrl &= ~(0x1 << num);
		*mpp_ctrl \|= sel << num;

		dove_mpp_gpio_mode(start, end, gpio_mode);
		}

		void __init dove_mpp_conf(unsigned int *mpp_list)
		/* Configure the group registers, enabling GPIO if sel indicates the
		pin is to be used for GPIO */
		static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
		{
		u32 mpp_ctrl[MPP_NR_REGS];
		u32 pmu_mpp_ctrl = 0;
		u32 pmu_sig_ctrl[PMU_SIG_REGS];
		int i;

		for (i = 0; i < MPP_NR_REGS; i++)
		mpp_ctrl[i] = readl(MPP_CTRL(i));

		for (i = 0; i < PMU_SIG_REGS; i++)
		pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));

		pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);

		dove_mpp_dump_regs();
		u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
		int gpio_mode;

		for ( ; *mpp_list != MPP_END; mpp_list++) {
		unsigned int num = MPP_NUM(*mpp_list);
		unsigned int sel = MPP_SEL(*mpp_list);
		int shift, gpio_mode;
		for ( ; *mpp_grp_list; mpp_grp_list++) {
		unsigned int num = MPP_NUM(*mpp_grp_list);
		unsigned int sel = MPP_SEL(*mpp_grp_list);

		if (num > MPP_MAX) {
		pr_err("dove: invalid MPP number (%u)\n", num);
		if (num > MPP_GRP_MAX) {
		pr_err("dove: invalid MPP GRP number (%u)\n", num);
		continue;
		}

		if (*mpp_list & MPP_NFC_MASK) {
		dove_mpp_cfg_nfc(sel);
		continue;
		}
		mpp_ctrl4 &= ~(0x1 << num);
		mpp_ctrl4 \|= sel << num;

		if (*mpp_list & MPP_AU1_MASK) {
		dove_mpp_cfg_au1(sel);
		continue;
		gpio_mode = sel ? GPIO_OUTPUT_OK \| GPIO_INPUT_OK : 0;
		dove_mpp_gpio_mode(dove_mpp_grp[num].start,
		dove_mpp_grp[num].end, gpio_mode);
		}

		if (*mpp_list & MPP_GRP_MASK) {
		dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
		continue;
		}

		shift = (num & 7) << 2;
		if (*mpp_list & MPP_PMU_MASK) {
		pmu_mpp_ctrl \|= (0x1 << num);
		pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
		pmu_sig_ctrl[num / 8] \|= 0xf << shift;
		gpio_mode = 0;
		} else {
		mpp_ctrl[num / 8] &= ~(0xf << shift);
		mpp_ctrl[num / 8] \|= sel << shift;
		gpio_mode = GPIO_OUTPUT_OK \| GPIO_INPUT_OK;
		}

		orion_gpio_set_valid(num, gpio_mode);
		writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
		}

		for (i = 0; i < MPP_NR_REGS; i++)
		writel(mpp_ctrl[i], MPP_CTRL(i));
		/* Configure the various MPP pins on Dove */
		void __init dove_mpp_conf(unsigned int *mpp_list,
		unsigned int *mpp_grp_list,
		unsigned int grp_au1_52_57,
		unsigned int grp_nfc_64_71)
		{
		dove_mpp_dump_regs();

		for (i = 0; i < PMU_SIG_REGS; i++)
		writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
		/* Use platform code for pins 0-23 */
		orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);

		writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
		dove_mpp_conf_grp(mpp_grp_list);
		dove_mpp_cfg_au1(grp_au1_52_57);
		dove_mpp_cfg_nfc(grp_nfc_64_71);

		dove_mpp_dump_regs();
		}

arch/arm/mach-dove/mpp.h

+169 −193

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-kirkwood/common.c

+32 −569

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-kirkwood/include/mach/irqs.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@
		#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
		#define IRQ_KIRKWOOD_GE00_ERR 46
		#define IRQ_KIRKWOOD_GE01_ERR 47
		#define IRQ_KIRKWOOD_RTC 53

		/*
		* KIRKWOOD General Purpose Pins