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Commit 1de4582f authored by Nick Hoath's avatar Nick Hoath Committed by Daniel Vetter
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drm/i915/gen9: Implement WaDisableDgMirrorFixInHalfSliceChicken5 



Move WaDisableDgMirrorFixInHalfSliceChicken5 to gen9_init_workarounds

v2: Added stepping check

v3: Removed unused register bitmap

Signed-off-by: default avatarNick Hoath <nicholas.hoath@intel.com>
[danvet: Bikesheds.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ab0dfafe

drivers/gpu/drm/i915/intel_pm.c

+0 −8
Original line number Diff line number Diff line
@@ -63,14 +63,6 @@ static void gen9_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/*

	 * WaDisableDgMirrorFixInHalfSliceChicken5:skl

	 * This is a pre-production w/a.

	 */

	I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,

		   I915_READ(GEN9_HALF_SLICE_CHICKEN5) &

		   ~GEN9_DG_MIRROR_FIX_ENABLE);



	/* Wa4x4STCOptimizationDisable:skl */

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));

drivers/gpu/drm/i915/intel_ringbuffer.c

+10 −0
Original line number Diff line number Diff line
@@ -882,6 +882,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) 
	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);



	if (INTEL_REVID(dev) == SKL_REVID_A0) {

		/*

		* WaDisableDgMirrorFixInHalfSliceChicken5:skl

		* This is a pre-production w/a.

		*/

		I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,

			I915_READ(GEN9_HALF_SLICE_CHICKEN5) &

			~GEN9_DG_MIRROR_FIX_ENABLE);

	}



	return 0;

}