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Commit 1d22a454 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx8: enable cp inst/reg error interrupts 



Enable CP register/instruction error interrupts. Useful
for debugging command stream problems.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a187f17f

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+10 −0
Original line number Diff line number Diff line
@@ -3901,6 +3901,8 @@ static int gfx_v8_0_hw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);

	gfx_v8_0_cp_enable(adev, false);

	gfx_v8_0_rlc_stop(adev);

	gfx_v8_0_cp_compute_fini(adev);
@@ -4329,6 +4331,14 @@ static int gfx_v8_0_late_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int r;



	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);

	if (r)

		return r;



	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);

	if (r)

		return r;



	/* requires IBs so do in late init after IB pool is initialized */

	r = gfx_v8_0_do_edc_gpr_workarounds(adev);

	if (r)