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Commit 1b9e6650 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Compact Gen8 semaphore initialization 



Replace the macro initializer with a programatic loop which
results in smaller code and hopefully just as clear.

v2: Rebase.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent db3d4019

drivers/gpu/drm/i915/intel_ringbuffer.c

+14 −2
Original line number Original line Diff line number Diff line
@@ -2888,7 +2888,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, 
				       struct intel_engine_cs *engine)

				       struct intel_engine_cs *engine)

{

{

	struct drm_i915_gem_object *obj;

	struct drm_i915_gem_object *obj;

	int ret;

	int ret, i;





	if (!i915_semaphore_is_enabled(dev_priv))

	if (!i915_semaphore_is_enabled(dev_priv))

		return;

		return;
@@ -2915,9 +2915,21 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, 
		return;

		return;





	if (INTEL_GEN(dev_priv) >= 8) {

	if (INTEL_GEN(dev_priv) >= 8) {

		u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);



		engine->semaphore.sync_to = gen8_ring_sync;

		engine->semaphore.sync_to = gen8_ring_sync;

		engine->semaphore.signal = gen8_xcs_signal;

		engine->semaphore.signal = gen8_xcs_signal;

		GEN8_RING_SEMAPHORE_INIT(engine);



		for (i = 0; i < I915_NUM_ENGINES; i++) {

			u64 ring_offset;



			if (i != engine->id)

				ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);

			else

				ring_offset = MI_SEMAPHORE_SYNC_INVALID;



			engine->semaphore.signal_ggtt[i] = ring_offset;

		}

	} else if (INTEL_GEN(dev_priv) >= 6) {

	} else if (INTEL_GEN(dev_priv) >= 6) {

		engine->semaphore.sync_to = gen6_ring_sync;

		engine->semaphore.sync_to = gen6_ring_sync;

		engine->semaphore.signal = gen6_signal;

		engine->semaphore.signal = gen6_signal;

drivers/gpu/drm/i915/intel_ringbuffer.h

+0 −12
Original line number Original line Diff line number Diff line
@@ -62,18 +62,6 @@ struct intel_hw_status_page { 
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \

	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \

	 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))

	 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))





#define GEN8_RING_SEMAPHORE_INIT(e) do { \

	if (!dev_priv->semaphore_obj) { \

		break; \

	} \

	(e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \

	(e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \

	(e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \

	(e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \

	(e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \

	(e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \

	} while(0)



enum intel_ring_hangcheck_action {

enum intel_ring_hangcheck_action {

	HANGCHECK_IDLE = 0,

	HANGCHECK_IDLE = 0,

	HANGCHECK_WAIT,

	HANGCHECK_WAIT,