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Commit 1b2538b2 authored by Mohammed Shafi Shajakhan's avatar Mohammed Shafi Shajakhan Committed by John W. Linville
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ath9k_hw: remove ATH9K_HW_CAP_CST 



its not used anywhere in the current code

Signed-off-by: default avatarMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 356cb55d

drivers/net/wireless/ath/ath9k/hw.c

+2 −4
Original line number Diff line number Diff line
@@ -2399,12 +2399,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) 
	else

		pCap->num_gpio_pins = AR_NUM_GPIO;



	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {

		pCap->hw_caps |= ATH9K_HW_CAP_CST;

	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))

		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;

	} else {

	else

		pCap->rts_aggr_limit = (8 * 1024);

	}



#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)

	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);

drivers/net/wireless/ath/ath9k/hw.h

+15 −16
Original line number Diff line number Diff line
@@ -196,22 +196,21 @@ enum ath_ini_subsys { 
enum ath9k_hw_caps {

	ATH9K_HW_CAP_HT                         = BIT(0),

	ATH9K_HW_CAP_RFSILENT                   = BIT(1),

	ATH9K_HW_CAP_CST                        = BIT(2),

	ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),

	ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),

	ATH9K_HW_CAP_EDMA			= BIT(6),

	ATH9K_HW_CAP_RAC_SUPPORTED		= BIT(7),

	ATH9K_HW_CAP_LDPC			= BIT(8),

	ATH9K_HW_CAP_FASTCLOCK			= BIT(9),

	ATH9K_HW_CAP_SGI_20			= BIT(10),

	ATH9K_HW_CAP_PAPRD			= BIT(11),

	ATH9K_HW_CAP_ANT_DIV_COMB		= BIT(12),

	ATH9K_HW_CAP_2GHZ			= BIT(13),

	ATH9K_HW_CAP_5GHZ			= BIT(14),

	ATH9K_HW_CAP_APM			= BIT(15),

	ATH9K_HW_CAP_RTT			= BIT(16),

	ATH9K_HW_CAP_MCI			= BIT(17),

	ATH9K_HW_CAP_DFS			= BIT(18),

	ATH9K_HW_CAP_AUTOSLEEP                  = BIT(2),

	ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(3),

	ATH9K_HW_CAP_EDMA			= BIT(4),

	ATH9K_HW_CAP_RAC_SUPPORTED		= BIT(5),

	ATH9K_HW_CAP_LDPC			= BIT(6),

	ATH9K_HW_CAP_FASTCLOCK			= BIT(7),

	ATH9K_HW_CAP_SGI_20			= BIT(8),

	ATH9K_HW_CAP_PAPRD			= BIT(9),

	ATH9K_HW_CAP_ANT_DIV_COMB		= BIT(10),

	ATH9K_HW_CAP_2GHZ			= BIT(11),

	ATH9K_HW_CAP_5GHZ			= BIT(12),

	ATH9K_HW_CAP_APM			= BIT(13),

	ATH9K_HW_CAP_RTT			= BIT(14),

	ATH9K_HW_CAP_MCI			= BIT(15),

	ATH9K_HW_CAP_DFS			= BIT(16),

};



struct ath9k_hw_capabilities {