Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1aa52bd3 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: fix tiling info on evergreen 



We aren't currently using tiling in userspace on evergreen,
but the info we currently return for the tiling info query
(gb_addr_config) is no adequate for userspace tiling alignment
calculations.  It does not contain the bank info.  Create a custom
tiling info dword with all the necessary info (num channels,
num banks, group size, row size).

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 268b2510

drivers/gpu/drm/radeon/evergreen.c

+30 −1
Original line number Original line Diff line number Diff line
@@ -1650,7 +1650,36 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		}

		}

	}

	}





	rdev->config.evergreen.tile_config = gb_addr_config;

	/* setup tiling info dword.  gb_addr_config is not adequate since it does

	 * not have bank info, so create a custom tiling dword.

	 * bits 3:0   num_pipes

	 * bits 7:4   num_banks

	 * bits 11:8  group_size

	 * bits 15:12 row_size

	 */

	rdev->config.evergreen.tile_config = 0;

	switch (rdev->config.evergreen.max_tile_pipes) {

	case 1:

	default:

		rdev->config.evergreen.tile_config |= (0 << 0);

		break;

	case 2:

		rdev->config.evergreen.tile_config |= (1 << 0);

		break;

	case 4:

		rdev->config.evergreen.tile_config |= (2 << 0);

		break;

	case 8:

		rdev->config.evergreen.tile_config |= (3 << 0);

		break;

	}

	rdev->config.evergreen.tile_config |=

		((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;

	rdev->config.evergreen.tile_config |=

		((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;

	rdev->config.evergreen.tile_config |=

		((gb_addr_config & 0x30000000) >> 28) << 12;



	WREG32(GB_BACKEND_MAP, gb_backend_map);

	WREG32(GB_BACKEND_MAP, gb_backend_map);

	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);