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Commit 1a5bbb66 authored by David Zhang's avatar David Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add Fiji support to the SDMA 3.0 IP module 



Signed-off-by: default avatarDavid Zhang <david1.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent af15a2d5

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+31 −0
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 
MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");

MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");

MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");

MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");

MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");



static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =

{
@@ -80,6 +82,24 @@ static const u32 tonga_mgcg_cgcg_init[] = 
	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100

};



static const u32 golden_settings_fiji_a10[] =

{

	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,

	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,

	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,

};



static const u32 fiji_mgcg_cgcg_init[] =

{

	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,

	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100

};



static const u32 cz_golden_settings_a11[] =

{

	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
@@ -122,6 +142,14 @@ static const u32 cz_mgcg_cgcg_init[] = 
static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_FIJI:

		amdgpu_program_register_sequence(adev,

						 fiji_mgcg_cgcg_init,

						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

						 golden_settings_fiji_a10,

						 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));

		break;

	case CHIP_TONGA:

		amdgpu_program_register_sequence(adev,

						 tonga_mgcg_cgcg_init,
@@ -167,6 +195,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 
	case CHIP_TONGA:

		chip_name = "tonga";

		break;

	case CHIP_FIJI:

		chip_name = "fiji";

		break;

	case CHIP_CARRIZO:

		chip_name = "carrizo";

		break;

drivers/gpu/drm/amd/amdgpu/vi.c

+7 −0
Original line number Diff line number Diff line
@@ -1209,6 +1209,13 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = 
		.rev = 0,

		.funcs = &gfx_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &sdma_v3_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version cz_ip_blocks[] =