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Commit 1a2f25d5 authored by Qipeng Zha's avatar Qipeng Zha Committed by Darren Hart
Browse files

intel_pmc_ipc: Fix GCR register base address and length 



GCR register (pmc_cfg register) is at offset 0x1008, and
remapping of 0x4 bytes is enough.

Signed-off-by: default avatarFrancois-Nicolas Muller <francois-nicolas.muller@intel.com>
Signed-off-by: default avatarQipeng Zha <qipeng.zha@intel.com>
Acked-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
parent 46707687

drivers/platform/x86/intel_pmc_ipc.c

+3 −2
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ 
/* exported resources from IFWI */

#define PLAT_RESOURCE_IPC_INDEX		0

#define PLAT_RESOURCE_IPC_SIZE		0x1000

#define PLAT_RESOURCE_GCR_SIZE		0x1000

#define PLAT_RESOURCE_GCR_OFFSET	0x1008

#define PLAT_RESOURCE_GCR_SIZE		0x4

#define PLAT_RESOURCE_BIOS_DATA_INDEX	1

#define PLAT_RESOURCE_BIOS_IFACE_INDEX	2

#define PLAT_RESOURCE_TELEM_SSRAM_INDEX	3
@@ -766,7 +767,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) 
	}

	ipcdev.ipc_base = addr;



	ipcdev.gcr_base = res->start + size;

	ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET;

	ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE;

	dev_info(&pdev->dev, "ipc res: %pR\n", res);