Commit 188237e2 authored Jul 02, 2008 by Saeed Bishara Committed by Nicolas Pitre Jul 07, 2008

[ARM] Feroceon: don't disable BPU on boot



On Feroceon platforms that have a branch prediction unit, bit 11 of the
cp15 control register controls the BPU.  This patch keeps the old value
of this bit instead of always clearing it.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

parent 2e1117d3

arch/arm/mm/proc-feroceon.S

+5 −4

Original line number	Diff line number	Diff line
		@@ -493,14 +493,15 @@ __feroceon_setup:
		.size __feroceon_setup, . - __feroceon_setup

		/*
		* R
		* .RVI ZFRS BLDP WCAM
		* .011 0001 ..11 0101
		* B
		* R P
		* .RVI UFRS BLDP WCAM
		* .011 .001 ..11 0101
		*
		*/
		.type feroceon_crval, #object
		feroceon_crval:
		crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
		crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134

		__INITDATA