Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 182434f7 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'exynos-cpuidle' of... 

Merge tag 'exynos-cpuidle' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung exynos-cpuidle updates for v3.16" from Kukjin Kim:

- From Daniel Lezcano:
 This patchset relies on the cpm_pm notifier to initiate the
 powerdown sequence operations from pm.c instead cpuidle.c.
 Thus the cpuidle driver is no longer dependent from arch
 specific code as everything is called from the pm.c file.

* tag 'exynos-cpuidle' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

: (94 commits)
  ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
  ARM: EXYNOS: Move the driver to drivers/cpuidle directory
  ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
  ARM: EXYNOS: Pass the AFTR callback to the platform_data
  ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
  ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
  ARM: EXYNOS: Move the AFTR state function into pm.c
  ARM: EXYNOS: Encapsulate the AFTR code into a function
  ARM: EXYNOS: Disable cpuidle for exynos5440
  ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
  ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
  ARM: EXYNOS: Remove ifdef for scu_enable in pm
  ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
  ARM: EXYNOS: Use the cpu_pm notifier for pm
  ARM: EXYNOS: Fix S5P_WAKEUP_STAT call for cpuidle
  ARM: EXYNOS: Move some code inside the idle_finisher for cpuidle
  ARM: EXYNOS: Encapsulate register access inside a function for pm
  ARM: EXYNOS: Change function name prefix for cpuidle
  ARM: EXYNOS: Use cpuidle_register
  ARM: EXYNOS: Prevent forward declaration for cpuidle
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 535cee42 cd245f59

Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
Samsung Exynos SYSRAM for SMP bringup:

------------------------------------



Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup

of the secondary cores. Once the core gets powered up it executes the

code that is residing at some specific location of the SYSRAM.



Therefore reserved section sub-nodes have to be added to the mmio-sram

declaration. These nodes are of two types depending upon secure or

non-secure execution environment.



Required sub-node properties:

- compatible : depending upon boot mode, should be

		"samsung,exynos4210-sysram" : for Secure SYSRAM

		"samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM



The rest of the properties should follow the generic mmio-sram discription

found in ../../misc/sysram.txt



Example:



	sysram@02020000 {

		compatible = "mmio-sram";

		reg = <0x02020000 0x54000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x02020000 0x54000>;



		smp-sysram@0 {

			compatible = "samsung,exynos4210-sysram";

			reg = <0x0 0x1000>;

		};



		smp-sysram@53000 {

			compatible = "samsung,exynos4210-sysram-ns";

			reg = <0x53000 0x1000>;

		};

	};

Documentation/devicetree/bindings/clock/exynos3250-clock.txt

0 → 100644
+41 −0
Original line number Diff line number Diff line 
* Samsung Exynos3250 Clock Controller



The Exynos3250 clock controller generates and supplies clock to various

controllers within the Exynos3250 SoC.



Required Properties:



- compatible: should be one of the following.

  - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume.



All available clocks are defined as preprocessor macros in

dt-bindings/clock/exynos3250.h header and can be used in device

tree sources.



Example 1: An example of a clock controller node is listed below.



	cmu: clock-controller@10030000 {

		compatible = "samsung,exynos3250-cmu";

		reg = <0x10030000 0x20000>;

		#clock-cells = <1>;

	};



Example 2: UART controller node that consumes the clock generated by the clock

	   controller. Refer to the standard clock bindings for information

	   about 'clocks' and 'clock-names' property.



	serial@13800000 {

		compatible = "samsung,exynos4210-uart";

		reg = <0x13800000 0x100>;

		interrupts = <0 109 0>;

		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;

		clock-names = "uart", "clk_uart_baud0";

	};

Documentation/devicetree/bindings/clock/exynos5260-clock.txt

0 → 100644
+190 −0
Original line number Diff line number Diff line 
* Samsung Exynos5260 Clock Controller



Exynos5260 has 13 clock controllers which are instantiated

independently from the device-tree. These clock controllers

generate and supply clocks to various hardware blocks within

the SoC.



Each clock is assigned an identifier and client nodes can use

this identifier to specify the clock which they consume. All

available clocks are defined as preprocessor macros in

dt-bindings/clock/exynos5260-clk.h header and can be used in

device tree sources.



External clocks:



There are several clocks that are generated outside the SoC. It

is expected that they are defined using standard clock bindings

with following clock-output-names:



 - "fin_pll" - PLL input clock from XXTI

 - "xrtcxti" - input clock from XRTCXTI

 - "ioclk_pcm_extclk" - pcm external operation clock

 - "ioclk_spdif_extclk" - spdif external operation clock

 - "ioclk_i2s_cdclk" - i2s0 codec clock



Phy clocks:



There are several clocks which are generated by specific PHYs.

These clocks are fed into the clock controller and then routed to

the hardware blocks. These clocks are defined as fixed clocks in the

driver with following names:



 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3

 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2

 - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1

 - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0

 - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock

 - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock

 - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link

 - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock

 - "phyclk_dptx_phy_clk_div2"

 - "phyclk_mipi_dphy_4l_m_rxclkesc0"

 - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock

 - "phyclk_usbhost20_phy_freeclk"

 - "phyclk_usbhost20_phy_clk48mohci"

 - "phyclk_usbdrd30_udrd30_pipe_pclk"

 - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock



Required Properties for Clock Controller:



 - compatible: should be one of the following.

	1) "samsung,exynos5260-clock-top"

	2) "samsung,exynos5260-clock-peri"

	3) "samsung,exynos5260-clock-egl"

	4) "samsung,exynos5260-clock-kfc"

	5) "samsung,exynos5260-clock-g2d"

	6) "samsung,exynos5260-clock-mif"

	7) "samsung,exynos5260-clock-mfc"

	8) "samsung,exynos5260-clock-g3d"

	9) "samsung,exynos5260-clock-fsys"

	10) "samsung,exynos5260-clock-aud"

	11) "samsung,exynos5260-clock-isp"

	12) "samsung,exynos5260-clock-gscl"

	13) "samsung,exynos5260-clock-disp"



 - reg: physical base address of the controller and the length of

	memory mapped region.



 - #clock-cells: should be 1.



 - clocks: list of clock identifiers which are fed as the input to

	the given clock controller. Please refer the next section to find

	the input clocks for a given controller.



 - clock-names: list of names of clocks which are fed as the input

	to the given clock controller.



Input clocks for top clock controller:

	- fin_pll

	- dout_mem_pll

	- dout_bus_pll

	- dout_media_pll



Input clocks for peri clock controller:

	- fin_pll

	- ioclk_pcm_extclk

	- ioclk_i2s_cdclk

	- ioclk_spdif_extclk

	- phyclk_hdmi_phy_ref_cko

	- dout_aclk_peri_66

	- dout_sclk_peri_uart0

	- dout_sclk_peri_uart1

	- dout_sclk_peri_uart2

	- dout_sclk_peri_spi0_b

	- dout_sclk_peri_spi1_b

	- dout_sclk_peri_spi2_b

	- dout_aclk_peri_aud

	- dout_sclk_peri_spi0_b



Input clocks for egl clock controller:

	- fin_pll

	- dout_bus_pll



Input clocks for kfc clock controller:

	- fin_pll

	- dout_media_pll



Input clocks for g2d clock controller:

	- fin_pll

	- dout_aclk_g2d_333



Input clocks for mif clock controller:

	- fin_pll



Input clocks for mfc clock controller:

	- fin_pll

	- dout_aclk_mfc_333



Input clocks for g3d clock controller:

	- fin_pll



Input clocks for fsys clock controller:

	- fin_pll

	- phyclk_usbhost20_phy_phyclock

	- phyclk_usbhost20_phy_freeclk

	- phyclk_usbhost20_phy_clk48mohci

	- phyclk_usbdrd30_udrd30_pipe_pclk

	- phyclk_usbdrd30_udrd30_phyclock

	- dout_aclk_fsys_200



Input clocks for aud clock controller:

	- fin_pll

	- fout_aud_pll

	- ioclk_i2s_cdclk

	- ioclk_pcm_extclk



Input clocks for isp clock controller:

	- fin_pll

	- dout_aclk_isp1_266

	- dout_aclk_isp1_400

	- mout_aclk_isp1_266



Input clocks for gscl clock controller:

	- fin_pll

	- dout_aclk_gscl_400

	- dout_aclk_gscl_333



Input clocks for disp clock controller:

	- fin_pll

	- phyclk_dptx_phy_ch3_txd_clk

	- phyclk_dptx_phy_ch2_txd_clk

	- phyclk_dptx_phy_ch1_txd_clk

	- phyclk_dptx_phy_ch0_txd_clk

	- phyclk_hdmi_phy_tmds_clko

	- phyclk_hdmi_phy_ref_clko

	- phyclk_hdmi_phy_pixel_clko

	- phyclk_hdmi_link_o_tmds_clkhi

	- phyclk_mipi_dphy_4l_m_txbyte_clkhs

	- phyclk_dptx_phy_o_ref_clk_24m

	- phyclk_dptx_phy_clk_div2

	- phyclk_mipi_dphy_4l_m_rxclkesc0

	- phyclk_hdmi_phy_ref_cko

	- ioclk_spdif_extclk

	- dout_aclk_peri_aud

	- dout_aclk_disp_222

	- dout_sclk_disp_pixel

	- dout_aclk_disp_333



Example 1: An example of a clock controller node is listed below.



	clock_mfc: clock-controller@11090000 {

		compatible = "samsung,exynos5260-clock-mfc";

		clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;

		clock-names = "fin_pll", "dout_aclk_mfc_333";

		reg = <0x11090000 0x10000>;

		#clock-cells = <1>;

	};



Example 2: UART controller node that consumes the clock generated by the

		peri clock controller. Refer to the standard clock bindings for

		information about 'clocks' and 'clock-names' property.



	serial@12C00000 {

		compatible = "samsung,exynos4210-uart";

		reg = <0x12C00000 0x100>;

		interrupts = <0 146 0>;

		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;

		clock-names = "uart", "clk_uart_baud0";

	};

Documentation/devicetree/bindings/clock/exynos5420-clock.txt

+2 −1
Original line number Diff line number Diff line 
* Samsung Exynos5420 Clock Controller



The Exynos5420 clock controller generates and supplies clock to various

controllers within the Exynos5420 SoC.

controllers within the Exynos5420 SoC and for the Exynos5800 SoC.



Required Properties:



- compatible: should be one of the following.

  - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.

  - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.



- reg: physical base address of the controller and length of memory mapped

  region.

Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt

0 → 100644
+50 −0
Original line number Diff line number Diff line 
* Samsung S3C2410 Clock Controller



The S3C2410 clock controller generates and supplies clock to various controllers

within the SoC. The clock binding described here is applicable to the s3c2410,

s3c2440 and s3c2442 SoCs in the s3c24x family.



Required Properties:



- compatible: should be one of the following.

  - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.

  - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.

  - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. Some of the clocks are available only

on a particular SoC.



All available clocks are defined as preprocessor macros in

dt-bindings/clock/s3c2410.h header and can be used in device

tree sources.



External clocks:



The xti clock used as input for the plls is generated outside the SoC. It is

expected that is are defined using standard clock bindings with a

clock-output-names value of "xti".



Example: Clock controller node:



	clocks: clock-controller@4c000000 {

		compatible = "samsung,s3c2410-clock";

		reg = <0x4c000000 0x20>;

		#clock-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller (refer to the standard clock bindings for information about

  "clocks" and "clock-names" properties):



	serial@50004000 {

		compatible = "samsung,s3c2440-uart";

		reg = <0x50004000 0x4000>;

		interrupts = <1 23 3 4>, <1 23 4 4>;

		clock-names = "uart", "clk_uart_baud2";

		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;

		status = "disabled";

	};