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Commit 1823f6d5 authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
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sh: sh7785 pll configuration from mode pin 



This patch modifies the sh7785 clock code to use the MODE4
value to switch between 72x and 36x PLL multiplication.

Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 63d12e23

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

+6 −6
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/cpufreq.h>

#include <asm/clock.h>

#include <asm/freq.h>

#include <cpu/sh7785.h>



static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,

			       24, 32, 36, 48 };
@@ -80,12 +81,11 @@ static struct clk_ops frqmr_clk_ops = { 


static unsigned long pll_recalc(struct clk *clk)

{

	/*

	 * XXX: PLL1 multiplier is locked for the default clock mode,

	 * when mode pin detection and configuration support is added,

	 * select the multiplier dynamically.

	 */

	return clk->parent->rate * 36;

	int multiplier;



	multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72;



	return clk->parent->rate * multiplier;

}



static struct clk_ops pll_clk_ops = {