Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 180076cb authored by Scott Wood's avatar Scott Wood Committed by Kumar Gala
Browse files

powerpc: Add fsl mpic timer binding 



Update the existing example in the general mpic binding to have a
separate TCRx region.  Currently the example doesn't describe TCRx at
all.  The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between.  That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.

Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.

Add fsl,available-ranges, similar to msi-available-ranges.

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent f46dad27

Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
* Freescale MPIC timers



Required properties:

- compatible: "fsl,mpic-global-timer"



- reg : Contains two regions.  The first is the main timer register bank

  (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx).  The second is the timer control

  register (TCRx) for the group.



- fsl,available-ranges: use <start count> style section to define which

  timer interrupts can be used.  This property is optional; without this,

  all timers within the group can be used.



- interrupts: one interrupt per timer in the group, in order, starting

  with timer zero.  If timer-available-ranges is present, only the

  interrupts that correspond to available timers shall be present.



Example:

	/* Note that this requires #interrupt-cells to be 4 */

	timer0: timer@41100 {

		compatible = "fsl,mpic-global-timer";

		reg = <0x41100 0x100 0x41300 4>;



		/* Another AMP partition is using timers 0 and 1 */

		fsl,available-ranges = <2 2>;



		interrupts = <2 0 3 0

		              3 0 3 0>;

	};



	timer1: timer@42100 {

		compatible = "fsl,mpic-global-timer";

		reg = <0x42100 0x100 0x42300 4>;

		interrupts = <4 0 3 0

		              5 0 3 0

		              6 0 3 0

		              7 0 3 0>;

	};

Documentation/devicetree/bindings/powerpc/fsl/mpic.txt

+1 −1
Original line number Diff line number Diff line
@@ -190,7 +190,7 @@ EXAMPLE 4 
	 */

	timer0: timer@41100 {

		compatible = "fsl,mpic-global-timer";

		reg = <0x41100 0x100>;

		reg = <0x41100 0x100 0x41300 4>;

		interrupts = <0 0 3 0

		              1 0 3 0

		              2 0 3 0