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Commit 17e6b00a authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "This updated pull request does not contain the last few GIC related
  patches which were reported to cause a regression.  There is a fix
  available, but I let it breed for a couple of days first.

  The irq departement provides:

   - new infrastructure to support non PCI based MSI interrupts
   - a couple of new irq chip drivers
   - the usual pile of fixlets and updates to irq chip drivers
   - preparatory changes for removal of the irq argument from interrupt
     flow handlers
   - preparatory changes to remove IRQF_VALID"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits)
  irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources
  irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2
  irqchip: Add documentation for the bcm2836 interrupt controller
  irqchip/bcm2835: Add support for being used as a second level controller
  irqchip/bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ
  PCI: xilinx: Fix typo in function name
  irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance
  irqchip/gic: Only allow the primary GIC to set the CPU map
  PCI/MSI: pci-xgene-msi: Consolidate chained IRQ handler install/remove
  unicore32/irq: Prepare puv3_gpio_handler for irq argument removal
  tile/pci_gx: Prepare trio_handle_level_irq for irq argument removal
  m68k/irq: Prepare irq handlers for irq argument removal
  C6X/megamode-pic: Prepare megamod_irq_cascade for irq argument removal
  blackfin: Prepare irq handlers for irq argument removal
  arc/irq: Prepare idu_cascade_isr for irq argument removal
  sparc/irq: Use access helper irq_data_get_affinity_mask()
  sparc/irq: Use helper irq_data_get_irq_handler_data()
  parisc/irq: Use access helper irq_data_get_affinity_mask()
  mn10300/irq: Use access helper irq_data_get_affinity_mask()
  irqchip/i8259: Prepare i8259_irq_dispatch for irq argument removal
  ...
parents 5e359bf2 e324c4dc

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

+24 −1
Original line number Diff line number Diff line
@@ -5,9 +5,14 @@ The BCM2835 contains a custom top-level interrupt controller, which supports 
controller, or the HW block containing it, is referred to occasionally

as "armctrl" in the SoC documentation, hence naming of this binding.



The BCM2836 contains the same interrupt controller with the same

interrupts, but the per-CPU interrupt controller is the root, and an

interrupt there indicates that the ARMCTRL has an interrupt to handle.



Required properties:



- compatible : should be "brcm,bcm2835-armctrl-ic"

- compatible : should be "brcm,bcm2835-armctrl-ic" or

                 "brcm,bcm2836-armctrl-ic"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an
@@ -20,6 +25,12 @@ Required properties: 
  The 2nd cell contains the interrupt number within the bank. Valid values

  are 0..7 for bank 0, and 0..31 for bank 1.



Additional required properties for brcm,bcm2836-armctrl-ic:

- interrupt-parent : Specifies the parent interrupt controller when this

  controller is the second level.

- interrupts : Specifies the interrupt on the parent for this interrupt

  controller to handle.



The interrupt sources are as follows:



Bank 0:
@@ -102,9 +113,21 @@ Bank 2: 


Example:



/* BCM2835, first level */

intc: interrupt-controller {

	compatible = "brcm,bcm2835-armctrl-ic";

	reg = <0x7e00b200 0x200>;

	interrupt-controller;

	#interrupt-cells = <2>;

};



/* BCM2836, second level */

intc: interrupt-controller {

	compatible = "brcm,bcm2836-armctrl-ic";

	reg = <0x7e00b200 0x200>;

	interrupt-controller;

	#interrupt-cells = <2>;



	interrupt-parent = <&local_intc>;

	interrupts = <8>;

};

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt

0 → 100644
+37 −0
Original line number Diff line number Diff line 
BCM2836 per-CPU interrupt controller



The BCM2836 has a per-cpu interrupt controller for the timer, PMU

events, and SMP IPIs.  One of the CPUs may receive interrupts for the

peripheral (GPU) events, which chain to the BCM2835-style interrupt

controller.



Required properties:



- compatible:	 	Should be "brcm,bcm2836-l1-intc"

- reg:			Specifies base physical address and size of the

			  registers

- interrupt-controller:	Identifies the node as an interrupt controller

- #interrupt-cells:	Specifies the number of cells needed to encode an

			  interrupt source. The value shall be 1



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.



The interrupt sources are as follows:



0: CNTPSIRQ

1: CNTPNSIRQ

2: CNTHPIRQ

3: CNTVIRQ

8: GPU_FAST

9: PMU_FAST



Example:



local_intc: local_intc {

	compatible = "brcm,bcm2836-l1-intc";

	reg = <0x40000000 0x100>;

	interrupt-controller;

	#interrupt-cells = <1>;

	interrupt-parent = <&local_intc>;

};

arch/alpha/kernel/irq.c

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ int irq_select_affinity(unsigned int irq) 
		cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);

	last_cpu = cpu;



	cpumask_copy(data->affinity, cpumask_of(cpu));

	cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));

	chip->irq_set_affinity(data, cpumask_of(cpu), false);

	return 0;

}

arch/arc/kernel/mcip.c

+2 −1
Original line number Diff line number Diff line
@@ -252,9 +252,10 @@ static struct irq_chip idu_irq_chip = { 


static int idu_first_irq;



static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc)

static void idu_cascade_isr(unsigned int __core_irq, struct irq_desc *desc)

{

	struct irq_domain *domain = irq_desc_get_handler_data(desc);

	unsigned int core_irq = irq_desc_get_irq(desc);

	unsigned int idu_irq;



	idu_irq = core_irq - idu_first_irq;

arch/arm/mach-shmobile/setup-r8a7779.c

+0 −2
Original line number Diff line number Diff line
@@ -62,8 +62,6 @@ static void __init r8a7779_map_io(void) 


static void __init r8a7779_init_irq_dt(void)

{

	gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);



	irqchip_init();



	/* route all interrupts to ARM */