Commit 178ca531 authored Jul 26, 2016 by Chen-Yu Tsai Committed by Maxime Ripard Aug 08, 2016

clk: sunxi-ng: mux: Increase fixed pre-divider div size



Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.

Increase the size of the div field to u16.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 29b4817d

drivers/clk/sunxi-ng/ccu_mux.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -18,7 +18,7 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
		int parent_index,
		unsigned long *parent_rate)
		{
		u8 prediv = 1;
		u16 prediv = 1;
		u32 reg;

		if (!((common->features & CCU_FEATURE_FIXED_PREDIV) \|\|

drivers/clk/sunxi-ng/ccu_mux.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -11,7 +11,7 @@ struct ccu_mux_internal {

		struct {
		u8 index;
		u8 div;
		u16 div;
		} fixed_prediv;

		struct {