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Commit 172e02d1 authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini
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MIPS: KVM: Sign extend MFC0/RDHWR results 



When emulating MFC0 instructions to load 32-bit values from guest COP0
registers and the RDHWR instruction to read the CC (Count) register,
sign extend the result to comply with the MIPS64 architecture. The
result must be in canonical 32-bit form or the guest may malfunction.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 5808844f

arch/mips/kvm/emulate.c

+4 −3
Original line number Diff line number Diff line
@@ -1072,14 +1072,15 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, 
#endif

			/* Get reg */

			if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {

				vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);

				vcpu->arch.gprs[rt] =

				    (s32)kvm_mips_read_count(vcpu);

			} else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {

				vcpu->arch.gprs[rt] = 0x0;

#ifdef CONFIG_KVM_MIPS_DYN_TRANS

				kvm_mips_trans_mfc0(inst, opc, vcpu);

#endif

			} else {

				vcpu->arch.gprs[rt] = cop0->reg[rd][sel];

				vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel];



#ifdef CONFIG_KVM_MIPS_DYN_TRANS

				kvm_mips_trans_mfc0(inst, opc, vcpu);
@@ -2380,7 +2381,7 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, 
					     current_cpu_data.icache.linesz);

			break;

		case MIPS_HWR_CC:		/* Read count register */

			arch->gprs[rt] = kvm_mips_read_count(vcpu);

			arch->gprs[rt] = (s32)kvm_mips_read_count(vcpu);

			break;

		case MIPS_HWR_CCRES:		/* Count register resolution */

			switch (current_cpu_data.cputype) {