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Commit 14fd8ed0 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Jason Cooper
Browse files

ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes 



Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.

Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent de1af8d4

arch/arm/boot/dts/armada-370-mirabox.dts

+16 −16
Original line number Diff line number Diff line
@@ -28,6 +28,22 @@ 
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000

			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;



		pcie-controller {

			status = "okay";



			/* Internal mini-PCIe connector */

			pcie@1,0 {

				/* Port 0, Lane 0 */

				status = "okay";

			};



			/* Connected on the PCB to a USB 3.0 XHCI controller */

			pcie@2,0 {

				/* Port 1, Lane 0 */

				status = "okay";

			};

		};



		internal-regs {

			serial@12000 {

				clock-frequency = <200000000>;
@@ -123,22 +139,6 @@ 
					reg = <0x25>;

				};

			};



			pcie-controller {

				status = "okay";



				/* Internal mini-PCIe connector */

				pcie@1,0 {

					/* Port 0, Lane 0 */

					status = "okay";

				};



				/* Connected on the PCB to a USB 3.0 XHCI controller */

				pcie@2,0 {

					/* Port 1, Lane 0 */

					status = "okay";

				};

			};

		};

	};

};

arch/arm/boot/dts/armada-370-xp.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ 
		#size-cells = <1>;

		controller = <&mbusc>;

		interrupt-parent = <&mpic>;

		pcie-mem-aperture = <0xe0000000 0x8000000>;

		pcie-io-aperture  = <0xe8000000 0x100000>;



		devbus-bootcs {

			compatible = "marvell,mvebu-devbus";

arch/arm/boot/dts/armada-370.dtsi

+53 −48
Original line number Diff line number Diff line
@@ -36,6 +36,59 @@ 
			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;

		};



		pcie-controller {

			compatible = "marvell,armada-370-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			ranges =

			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000

				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000

				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */

				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */

				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */

				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0

                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &mpic 58>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gateclk 5>;

				status = "disabled";

			};



			pcie@2,0 {

				device_type = "pci";

				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;

				reg = <0x1000 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0

                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &mpic 62>;

				marvell,pcie-port = <1>;

				marvell,pcie-lane = <0>;

				clocks = <&gateclk 9>;

				status = "disabled";

			};

		};



		internal-regs {

			system-controller@18200 {

				compatible = "marvell,armada-370-xp-system-controller";
@@ -174,54 +227,6 @@ 
					0x18304 0x4>;

				status = "okay";

			};



			pcie-controller {

				compatible = "marvell,armada-370-pcie";

				status = "disabled";

				device_type = "pci";



				#address-cells = <3>;

				#size-cells = <2>;



				bus-range = <0x00 0xff>;



				ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */

					0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */

					0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */

					0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */



				pcie@1,0 {

					device_type = "pci";

					assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;

					reg = <0x0800 0 0 0 0>;

					#address-cells = <3>;

					#size-cells = <2>;

					#interrupt-cells = <1>;

					ranges;

					interrupt-map-mask = <0 0 0 0>;

					interrupt-map = <0 0 0 0 &mpic 58>;

					marvell,pcie-port = <0>;

					marvell,pcie-lane = <0>;

					clocks = <&gateclk 5>;

					status = "disabled";

				};



				pcie@2,0 {

					device_type = "pci";

					assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;

					reg = <0x1000 0 0 0 0>;

					#address-cells = <3>;

					#size-cells = <2>;

					#interrupt-cells = <1>;

					ranges;

					interrupt-map-mask = <0 0 0 0>;

					interrupt-map = <0 0 0 0 &mpic 62>;

					marvell,pcie-port = <1>;

					marvell,pcie-lane = <0>;

					clocks = <&gateclk 9>;

					status = "disabled";

				};

			};

		};

	};

};

arch/arm/boot/dts/armada-xp-db.dts

+33 −34
Original line number Diff line number Diff line
@@ -62,6 +62,39 @@ 
			};

		};



		pcie-controller {

			status = "okay";



			/*

			 * All 6 slots are physically present as

			 * standard PCIe slots on the board.

			 */

			pcie@1,0 {

				/* Port 0, Lane 0 */

				status = "okay";

			};

			pcie@2,0 {

				/* Port 0, Lane 1 */

				status = "okay";

			};

			pcie@3,0 {

				/* Port 0, Lane 2 */

				status = "okay";

			};

			pcie@4,0 {

				/* Port 0, Lane 3 */

				status = "okay";

			};

			pcie@9,0 {

				/* Port 2, Lane 0 */

				status = "okay";

			};

			pcie@10,0 {

				/* Port 3, Lane 0 */

				status = "okay";

			};

		};



		internal-regs {

			serial@12000 {

				clock-frequency = <250000000>;
@@ -155,40 +188,6 @@ 
					spi-max-frequency = <20000000>;

				};

			};



			pcie-controller {

				status = "okay";



				/*

				 * All 6 slots are physically present as

				 * standard PCIe slots on the board.

				 */

				pcie@1,0 {

					/* Port 0, Lane 0 */

					status = "okay";

				};

				pcie@2,0 {

					/* Port 0, Lane 1 */

					status = "okay";

				};

				pcie@3,0 {

					/* Port 0, Lane 2 */

					status = "okay";

				};

				pcie@4,0 {

					/* Port 0, Lane 3 */

					status = "okay";

				};

				pcie@9,0 {

					/* Port 2, Lane 0 */

					status = "okay";

				};

				pcie@10,0 {

					/* Port 3, Lane 0 */

					status = "okay";

				};

			};



		};

	};

};

arch/arm/boot/dts/armada-xp-gp.dts

+21 −21
Original line number Diff line number Diff line
@@ -71,6 +71,27 @@ 
			};

		};



		pcie-controller {

			status = "okay";



			/*

			 * The 3 slots are physically present as

			 * standard PCIe slots on the board.

			 */

			pcie@1,0 {

				/* Port 0, Lane 0 */

				status = "okay";

			};

			pcie@9,0 {

				/* Port 2, Lane 0 */

				status = "okay";

			};

			pcie@10,0 {

				/* Port 3, Lane 0 */

				status = "okay";

			};

		};



		internal-regs {

			serial@12000 {

				clock-frequency = <250000000>;
@@ -154,27 +175,6 @@ 
					spi-max-frequency = <108000000>;

				};

			};



			pcie-controller {

				status = "okay";



				/*

				 * The 3 slots are physically present as

				 * standard PCIe slots on the board.

				 */

				pcie@1,0 {

					/* Port 0, Lane 0 */

					status = "okay";

				};

				pcie@9,0 {

					/* Port 2, Lane 0 */

					status = "okay";

				};

				pcie@10,0 {

					/* Port 3, Lane 0 */

					status = "okay";

				};

			};

		};

	};

};