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Commit 14eff181 authored by Daniel Walker's avatar Daniel Walker Committed by Russell King
Browse files

ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM 



Setting of these bits can cause issues on other SMP SoC's not produced
by ARM.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b2b163bb

arch/arm/mm/proc-v7.S

+25 −1
Original line number Diff line number Diff line
@@ -186,13 +186,14 @@ cpu_v7_name: 
 *	It is assumed that:

 *	- cache type register is implemented

 */

__v7_setup:

__v7_ca9mp_setup:

#ifdef CONFIG_SMP

	mrc	p15, 0, r0, c1, c0, 1

	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?

	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and

	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting

#endif

__v7_setup:

	adr	r12, __v7_setup_stack		@ the local stack

	stmia	r12, {r0-r5, r7, r9, r11, lr}

	bl	v7_flush_dcache_all
@@ -349,6 +350,29 @@ cpu_elf_name: 


	.section ".proc.info.init", #alloc, #execinstr



	.type   __v7_ca9mp_proc_info, #object

__v7_ca9mp_proc_info:

	.long	0x410fc090		@ Required ID value

	.long	0xff0ffff0		@ Mask for ID

	.long   PMD_TYPE_SECT | \

		PMD_SECT_AP_WRITE | \

		PMD_SECT_AP_READ | \

		PMD_FLAGS

	.long   PMD_TYPE_SECT | \

		PMD_SECT_XN | \

		PMD_SECT_AP_WRITE | \

		PMD_SECT_AP_READ

	b	__v7_ca9mp_setup

	.long	cpu_arch_name

	.long	cpu_elf_name

	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP

	.long	cpu_v7_name

	.long	v7_processor_functions

	.long	v7wbi_tlb_fns

	.long	v6_user_fns

	.long	v7_cache_fns

	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info



	/*

	 * Match any ARMv7 processor core.

	 */