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Commit 149e9ab4 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller
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driver: net: xgene: Add support for 2nd 10GbE port 



Adding support for the second 10GbE port on APM X-Gene SoC

Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7b6ee48d

drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

+2 −1
Original line number Diff line number Diff line
@@ -107,7 +107,8 @@ static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring) 
{

	xgene_enet_ring_set_type(ring);



	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0)

	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||

	    xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)

		xgene_enet_ring_set_recombbuf(ring);



	xgene_enet_ring_init(ring);

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

+12 −4
Original line number Diff line number Diff line
@@ -1305,10 +1305,17 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) 
			pdata->ring_num = START_RING_NUM_0;

			break;

		case 1:

			if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {

				pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;

				pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;

				pdata->bp_bufnum = XG_START_BP_BUFNUM_1;

				pdata->ring_num = XG_START_RING_NUM_1;

			} else {

				pdata->cpu_bufnum = START_CPU_BUFNUM_1;

				pdata->eth_bufnum = START_ETH_BUFNUM_1;

				pdata->bp_bufnum = START_BP_BUFNUM_1;

				pdata->ring_num = START_RING_NUM_1;

			}

			break;

		default:

			break;
@@ -1478,6 +1485,7 @@ static const struct acpi_device_id xgene_enet_acpi_match[] = { 
	{ "APMC0D05", XGENE_ENET1},

	{ "APMC0D30", XGENE_ENET1},

	{ "APMC0D31", XGENE_ENET1},

	{ "APMC0D3F", XGENE_ENET1},

	{ "APMC0D26", XGENE_ENET2},

	{ "APMC0D25", XGENE_ENET2},

	{ }

drivers/net/ethernet/apm/xgene/xgene_enet_main.h

+5 −0
Original line number Diff line number Diff line
@@ -56,6 +56,11 @@ 
#define START_BP_BUFNUM_1	0x2A

#define START_RING_NUM_1	264



#define XG_START_CPU_BUFNUM_1	12

#define XG_START_ETH_BUFNUM_1	2

#define XG_START_BP_BUFNUM_1	0x22

#define XG_START_RING_NUM_1	264



#define X2_START_CPU_BUFNUM_0	0

#define X2_START_ETH_BUFNUM_0	0

#define X2_START_BP_BUFNUM_0	0x20