Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1446f17a authored by Borislav Petkov's avatar Borislav Petkov
Browse files

Merge tag 'edac_calxeda_for_3.13' into edac-for-3.13 

Pull Calxeda Highbank stuff from Robert Richter.
parents 959f5854 78cfbf0b

Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt

+3 −1
Original line number Diff line number Diff line 
Calxeda DDR memory controller



Properties:

- compatible : Should be "calxeda,hb-ddr-ctrl"

- compatible : Should be:

  - "calxeda,hb-ddr-ctrl" for ECX-1000

  - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000

- reg : Address and size for DDR controller registers.

- interrupts : Interrupt for DDR controller.

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -3047,6 +3047,14 @@ W: bluesmoke.sourceforge.net 
S:	Maintained

F:	drivers/edac/amd64_edac*



EDAC-CALXEDA

M:	Doug Thompson <dougthompson@xmission.com>

M:	Robert Richter <rric@kernel.org>

L:	linux-edac@vger.kernel.org

W:	bluesmoke.sourceforge.net

S:	Maintained

F:	drivers/edac/highbank*



EDAC-CAVIUM

M:	Ralf Baechle <ralf@linux-mips.org>

M:	David Daney <david.daney@cavium.com>

arch/arm/boot/dts/ecx-2000.dts

+6 −0
Original line number Diff line number Diff line
@@ -85,6 +85,12 @@ 
				<1 10 0xf08>;

		};



		memory-controller@fff00000 {

			compatible = "calxeda,ecx-2000-ddr-ctrl";

			reg = <0xfff00000 0x1000>;

			interrupts = <0 91 4>;

		};



		intc: interrupt-controller@fff11000 {

			compatible = "arm,cortex-a15-gic";

			#interrupt-cells = <3>;

arch/arm/boot/dts/ecx-common.dtsi

+0 −6
Original line number Diff line number Diff line
@@ -45,12 +45,6 @@ 
			status = "disabled";

		};



		memory-controller@fff00000 {

			compatible = "calxeda,hb-ddr-ctrl";

			reg = <0xfff00000 0x1000>;

			interrupts = <0 91 4>;

		};



		ipc@fff20000 {

			compatible = "arm,pl320", "arm,primecell";

			reg = <0xfff20000 0x1000>;

arch/arm/boot/dts/highbank.dts

+6 −0
Original line number Diff line number Diff line
@@ -86,6 +86,12 @@ 
	soc {

		ranges = <0x00000000 0x00000000 0xffffffff>;



		memory-controller@fff00000 {

			compatible = "calxeda,hb-ddr-ctrl";

			reg = <0xfff00000 0x1000>;

			interrupts = <0 91 4>;

		};



		timer@fff10600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xfff10600 0x20>;