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Commit 143a8307 authored by Andrew Lunn's avatar Andrew Lunn Committed by David S. Miller
Browse files

net: dsa: Centralize Marvell switch reset 



Marvell switches are all reset in nearly the same way. The only
difference is if the PPU should be enabled or not. Move this
code into the shared mv88x6xxx.c.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Tested-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 44e50ddb

drivers/net/dsa/mv88e6123_61_65.c

+1 −35
Original line number Diff line number Diff line
@@ -52,40 +52,6 @@ static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) 
	return NULL;

}



static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;

	unsigned long timeout;



	/* Set all ports to the disabled state. */

	for (i = 0; i < ps->num_ports; i++) {

		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);

	}



	/* Wait for transmit queues to drain. */

	usleep_range(2000, 4000);



	/* Reset the switch. */

	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);



	/* Wait up to one second for reset to complete. */

	timeout = jiffies + 1 * HZ;

	while (time_before(jiffies, timeout)) {

		ret = REG_READ(REG_GLOBAL, 0x00);

		if ((ret & 0xc800) == 0xc800)

			break;



		usleep_range(1000, 2000);

	}

	if (time_after(jiffies, timeout))

		return -ETIMEDOUT;



	return 0;

}



static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)

{

	int ret;
@@ -292,7 +258,7 @@ static int mv88e6123_61_65_setup(struct dsa_switch *ds) 
		return -ENODEV;

	}



	ret = mv88e6123_61_65_switch_reset(ds);

	ret = mv88e6xxx_switch_reset(ds, false);

	if (ret < 0)

		return ret;

drivers/net/dsa/mv88e6131.c

+1 −35
Original line number Diff line number Diff line
@@ -42,40 +42,6 @@ static char *mv88e6131_probe(struct device *host_dev, int sw_addr) 
	return NULL;

}



static int mv88e6131_switch_reset(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;

	unsigned long timeout;



	/* Set all ports to the disabled state. */

	for (i = 0; i < ps->num_ports; i++) {

		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);

	}



	/* Wait for transmit queues to drain. */

	usleep_range(2000, 4000);



	/* Reset the switch. */

	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);



	/* Wait up to one second for reset to complete. */

	timeout = jiffies + 1 * HZ;

	while (time_before(jiffies, timeout)) {

		ret = REG_READ(REG_GLOBAL, 0x00);

		if ((ret & 0xc800) == 0xc800)

			break;



		usleep_range(1000, 2000);

	}

	if (time_after(jiffies, timeout))

		return -ETIMEDOUT;



	return 0;

}



static int mv88e6131_setup_global(struct dsa_switch *ds)

{

	int ret;
@@ -281,7 +247,7 @@ static int mv88e6131_setup(struct dsa_switch *ds) 
		return -ENODEV;

	}



	ret = mv88e6131_switch_reset(ds);

	ret = mv88e6xxx_switch_reset(ds, false);

	if (ret < 0)

		return ret;

drivers/net/dsa/mv88e6171.c

+1 −47
Original line number Diff line number Diff line
@@ -36,52 +36,6 @@ static char *mv88e6171_probe(struct device *host_dev, int sw_addr) 
	return NULL;

}



static int mv88e6171_switch_reset(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;

	unsigned long timeout;



	/* Set all ports to the disabled state. */

	for (i = 0; i < ps->num_ports; i++) {

		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);

	}



	/* Wait for transmit queues to drain. */

	usleep_range(2000, 4000);



	/* Reset the switch. Keep PPU active.  The PPU needs to be

	 * active to support indirect phy register accesses through

	 * global registers 0x18 and 0x19.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0xc000);



	/* Wait up to one second for reset to complete. */

	timeout = jiffies + 1 * HZ;

	while (time_before(jiffies, timeout)) {

		ret = REG_READ(REG_GLOBAL, 0x00);

		if ((ret & 0xc800) == 0xc800)

			break;



		usleep_range(1000, 2000);

	}

	if (time_after(jiffies, timeout))

		return -ETIMEDOUT;



	/* Enable ports not under DSA, e.g. WAN port */

	for (i = 0; i < ps->num_ports; i++) {

		if (dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i))

			continue;



		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret | 0x03);

	}



	return 0;

}



static int mv88e6171_setup_global(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -282,7 +236,7 @@ static int mv88e6171_setup(struct dsa_switch *ds) 


	ps->num_ports = 7;



	ret = mv88e6171_switch_reset(ds);

	ret = mv88e6xxx_switch_reset(ds, true);

	if (ret < 0)

		return ret;

drivers/net/dsa/mv88e6352.c

+1 −37
Original line number Diff line number Diff line
@@ -45,42 +45,6 @@ static char *mv88e6352_probe(struct device *host_dev, int sw_addr) 
	return NULL;

}



static int mv88e6352_switch_reset(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	unsigned long timeout;

	int ret;

	int i;



	/* Set all ports to the disabled state. */

	for (i = 0; i < ps->num_ports; i++) {

		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);

	}



	/* Wait for transmit queues to drain. */

	usleep_range(2000, 4000);



	/* Reset the switch. Keep PPU active (bit 14, undocumented).

	 * The PPU needs to be active to support indirect phy register

	 * accesses through global registers 0x18 and 0x19.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0xc000);



	/* Wait up to one second for reset to complete. */

	timeout = jiffies + 1 * HZ;

	while (time_before(jiffies, timeout)) {

		ret = REG_READ(REG_GLOBAL, 0x00);

		if ((ret & 0x8800) == 0x8800)

			break;

		usleep_range(1000, 2000);

	}

	if (time_after(jiffies, timeout))

		return -ETIMEDOUT;



	return 0;

}



static int mv88e6352_setup_global(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
@@ -373,7 +337,7 @@ static int mv88e6352_setup(struct dsa_switch *ds) 


	mutex_init(&ps->eeprom_mutex);



	ret = mv88e6352_switch_reset(ds);

	ret = mv88e6xxx_switch_reset(ds, true);

	if (ret < 0)

		return ret;

drivers/net/dsa/mv88e6xxx.c

+40 −0
Original line number Diff line number Diff line
@@ -1161,6 +1161,46 @@ int mv88e6xxx_setup_common(struct dsa_switch *ds) 
	return 0;

}



int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	u16 is_reset = (ppu_active ? 0x8800 : 0xc800);

	unsigned long timeout;

	int ret;

	int i;



	/* Set all ports to the disabled state. */

	for (i = 0; i < ps->num_ports; i++) {

		ret = REG_READ(REG_PORT(i), 0x04);

		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);

	}



	/* Wait for transmit queues to drain. */

	usleep_range(2000, 4000);



	/* Reset the switch. Keep the PPU active if requested. The PPU

	 * needs to be active to support indirect phy register access

	 * through global registers 0x18 and 0x19.

	 */

	if (ppu_active)

		REG_WRITE(REG_GLOBAL, 0x04, 0xc000);

	else

		REG_WRITE(REG_GLOBAL, 0x04, 0xc400);



	/* Wait up to one second for reset to complete. */

	timeout = jiffies + 1 * HZ;

	while (time_before(jiffies, timeout)) {

		ret = REG_READ(REG_GLOBAL, 0x00);

		if ((ret & is_reset) == is_reset)

			break;

		usleep_range(1000, 2000);

	}

	if (time_after(jiffies, timeout))

		return -ETIMEDOUT;



	return 0;

}



static int __init mv88e6xxx_init(void)

{

#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)