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Commit 13b3a0a7 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Mask the vblank interrupt on bdw by default 



Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 38d83c96

drivers/gpu/drm/i915/i915_irq.c

+8 −8
Original line number Diff line number Diff line
@@ -2917,15 +2917,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;

	uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |

				   GEN8_PIPE_VBLANK |

	uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |

		GEN8_PIPE_CDCLK_CRC_DONE |

		GEN8_PIPE_FIFO_UNDERRUN |

		GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

	uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;

	int pipe;

	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;

	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;

	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;

	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;

	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;

	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;



	for_each_pipe(pipe) {

		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));