Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 139d6065 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 

Conflicts:
	drivers/net/wireless/iwlwifi/iwl-rx.c
parents efb064de b37fa870

drivers/net/wireless/ath/ar9170/usb.c

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ static struct usb_device_id ar9170_usb_ids[] = { 
	{ USB_DEVICE(0x0cf3, 0x9170) },

	/* Atheros TG121N */

	{ USB_DEVICE(0x0cf3, 0x1001) },

	/* TP-Link TL-WN821N v2 */

	{ USB_DEVICE(0x0cf3, 0x1002) },

	/* Cace Airpcap NX */

	{ USB_DEVICE(0xcace, 0x0300) },

	/* D-Link DWA 160A */

drivers/net/wireless/ath/ath9k/calib.c

+18 −5
Original line number Diff line number Diff line
@@ -609,14 +609,24 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) 
		AR_PHY_CH1_EXT_CCA,

		AR_PHY_CH2_EXT_CCA

	};

	u8 chainmask;

	u8 chainmask, rx_chain_status;



	rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);

	if (AR_SREV_9285(ah))

		chainmask = 0x9;

	else if (AR_SREV_9280(ah) || AR_SREV_9287(ah))

	else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {

		if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))

			chainmask = 0x1B;

		else

			chainmask = 0x09;

	} else {

		if (rx_chain_status & 0x4)

			chainmask = 0x3F;

		else if (rx_chain_status & 0x2)

			chainmask = 0x1B;

		else

			chainmask = 0x09;

	}



	h = ah->nfCalHist;
@@ -697,6 +707,8 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah) 
		noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;

	else if (AR_SREV_9285(ah))

		noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;

	else if (AR_SREV_9287(ah))

		noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;

	else

		noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
@@ -924,6 +936,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) 
		regVal |= (1 << (19 + i));

		REG_WRITE(ah, 0x7834, regVal);

		udelay(1);

		regVal = REG_READ(ah, 0x7834);

		regVal &= (~(0x1 << (19 + i)));

		reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);

		regVal |= (reg_field << (19 + i));

drivers/net/wireless/ath/ath9k/calib.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ extern const struct ath9k_percal_data adc_init_dc_cal; 
#define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE	-85

#define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE	-112

#define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE	-118

#define AR_PHY_CCA_MAX_AR9287_GOOD_VALUE	-118

#define AR_PHY_CCA_MAX_HIGH_VALUE      		-62

#define AR_PHY_CCA_MIN_BAD_VALUE       		-140

#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT     3

drivers/net/wireless/ath/ath9k/eeprom_def.c

+3 −1
Original line number Diff line number Diff line
@@ -509,6 +509,8 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah, 
			REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,

				      eep->baseEepHeader.dacLpMode);



		udelay(100);



		REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,

			      pModal->miscBits >> 2);
@@ -902,7 +904,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, 
						  u16 powerLimit)

{

#define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */

#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */

#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */



	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;

drivers/net/wireless/ath/ath9k/hw.c

+121 −81
Original line number Diff line number Diff line
@@ -842,7 +842,7 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 


static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)

{

	if (AR_SREV_9287_11(ah))

	if (AR_SREV_9287_11_OR_LATER(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

		ar9287Modes_rx_gain_9287_1_1,

		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
@@ -853,7 +853,7 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 
	else if (AR_SREV_9280_20(ah))

		ath9k_hw_init_rxgain_ini(ah);



	if (AR_SREV_9287_11(ah)) {

	if (AR_SREV_9287_11_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ah->iniModesTxGain,

		ar9287Modes_tx_gain_9287_1_1,

		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
@@ -965,7 +965,7 @@ int ath9k_hw_init(struct ath_hw *ah) 
	ath9k_hw_init_mode_regs(ah);



	if (ah->is_pciexpress)

		ath9k_hw_configpcipowersave(ah, 0);

		ath9k_hw_configpcipowersave(ah, 0, 0);

	else

		ath9k_hw_disablepcie(ah);
@@ -1273,6 +1273,15 @@ static void ath9k_hw_override_ini(struct ath_hw *ah, 
	 */

	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));



	if (AR_SREV_9280_10_OR_LATER(ah)) {

		val = REG_READ(ah, AR_PCU_MISC_MODE2) &

			       (~AR_PCU_MISC_MODE2_HWWAR1);



		if (AR_SREV_9287_10_OR_LATER(ah))

			val = val & (~AR_PCU_MISC_MODE2_HWWAR2);



		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);

	}



	if (!AR_SREV_5416_20_OR_LATER(ah) ||

	    AR_SREV_9280_10_OR_LATER(ah))
@@ -1784,7 +1793,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 
static bool ath9k_hw_chip_reset(struct ath_hw *ah,

				struct ath9k_channel *chan)

{

	if (OLC_FOR_AR9280_20_LATER) {

	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {

		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))

			return false;

	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
@@ -2338,6 +2347,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	struct ath9k_channel *curchan = ah->curchan;

	u32 saveDefAntenna;

	u32 macStaId1;

	u64 tsf = 0;

	int i, rx_chainmask, r;



	ah->extprotspacing = sc->ht_extprotspacing;
@@ -2347,7 +2357,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))

		return -EIO;



	if (curchan)

	if (curchan && !ah->chip_fullsleep)

		ath9k_hw_getnf(ah, curchan);



	if (bChannelChange &&
@@ -2356,8 +2366,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	    (chan->channel != ah->curchan->channel) &&

	    ((chan->channelFlags & CHANNEL_ALL) ==

	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&

	    (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&

				   !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {

	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||

	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {



		if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {

			ath9k_hw_loadnf(ah, ah->curchan);
@@ -2372,6 +2382,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 


	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;



	/* For chips on which RTC reset is done, save TSF before it gets cleared */

	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))

		tsf = ath9k_hw_gettsf64(ah);



	saveLedState = REG_READ(ah, AR_CFG_LED) &

		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |

		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
@@ -2398,6 +2412,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
		udelay(50);

	}



	/* Restore TSF */

	if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))

		ath9k_hw_settsf64(ah, tsf);



	if (AR_SREV_9280_10_OR_LATER(ah))

		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
@@ -3005,9 +3023,10 @@ void ath9k_ps_restore(struct ath_softc *sc) 
 * Programming the SerDes must go through the same 288 bit serial shift

 * register as the other analog registers.  Hence the 9 writes.

 */

void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)

void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)

{

	u8 i;

	u32 val;



	if (ah->is_pciexpress != true)

		return;
@@ -3017,9 +3036,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) 
		return;



	/* Nothing to do on restore for 11N */

	if (restore)

		return;



	if (!restore) {

		if (AR_SREV_9280_20_OR_LATER(ah)) {

			/*

			 * AR9280 2.0 or later chips use SerDes values from the
@@ -3083,18 +3100,49 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) 


		/* Several PCIe massages to ensure proper behaviour */

		if (ah->config.pcie_waen) {

		REG_WRITE(ah, AR_WA, ah->config.pcie_waen);

			val = ah->config.pcie_waen;

			if (!power_off)

				val &= (~AR_WA_D3_L1_DISABLE);

		} else {

		if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))

			REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);

			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||

			    AR_SREV_9287(ah)) {

				val = AR9285_WA_DEFAULT;

				if (!power_off)

					val &= (~AR_WA_D3_L1_DISABLE);

			} else if (AR_SREV_9280(ah)) {

				/*

		 * On AR9280 chips bit 22 of 0x4004 needs to be set to

		 * otherwise card may disappear.

				 * On AR9280 chips bit 22 of 0x4004 needs to be

				 * set otherwise card may disappear.

				 */

		else if (AR_SREV_9280(ah))

			REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);

		else

			REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);

				val = AR9280_WA_DEFAULT;

				if (!power_off)

					val &= (~AR_WA_D3_L1_DISABLE);

			} else

				val = AR_WA_DEFAULT;

		}



		REG_WRITE(ah, AR_WA, val);

	}



	if (power_off) {

		/*

		 * Set PCIe workaround bits

		 * bit 14 in WA register (disable L1) should only

		 * be set when device enters D3 and be cleared

		 * when device comes back to D0.

		 */

		if (ah->config.pcie_waen) {

			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)

				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);

		} else {

			if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||

			      AR_SREV_9287(ah)) &&

			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||

			    (AR_SREV_9280(ah) &&

			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {

				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);

			}

		}

	}

}
@@ -3652,15 +3700,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah) 
	}

#endif



	if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||

	    (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||

	    (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||

	    (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||

	    (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||

	    (ah->hw_version.macVersion == AR_SREV_VERSION_9285))

	pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;

	else

		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;



	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))

		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;