MN10300: Convert cpu irq_chips to new functions (125bb1db) · Commits · e / devices / android_kernel_teracube_2e

arch/mn10300/kernel/irq.c

+33 −29

Original line number	Diff line number	Diff line
		@@ -37,8 +37,9 @@ atomic_t irq_err_count;
		/*
		* MN10300 interrupt controller operations
		*/
		static void mn10300_cpupic_ack(unsigned int irq)
		static void mn10300_cpupic_ack(struct irq_data *d)
		{
		unsigned int irq = d->irq;
		unsigned long flags;
		u16 tmp;

		@@ -61,13 +62,14 @@ static void __mask_and_set_icr(unsigned int irq,
		arch_local_irq_restore(flags);
		}

		static void mn10300_cpupic_mask(unsigned int irq)
		static void mn10300_cpupic_mask(struct irq_data *d)
		{
		__mask_and_set_icr(irq, GxICR_LEVEL, 0);
		__mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
		}

		static void mn10300_cpupic_mask_ack(unsigned int irq)
		static void mn10300_cpupic_mask_ack(struct irq_data *d)
		{
		unsigned int irq = d->irq;
		#ifdef CONFIG_SMP
		unsigned long flags;
		u16 tmp;
		@@ -85,7 +87,7 @@ static void mn10300_cpupic_mask_ack(unsigned int irq)
		tmp2 = GxICR(irq);

		irq_affinity_online[irq] =
		any_online_cpu(*irq_desc[irq].affinity);
		any_online_cpu(*d->affinity);
		CROSS_GxICR(irq, irq_affinity_online[irq]) =
		(tmp & (GxICR_LEVEL \| GxICR_ENABLE)) \| GxICR_DETECT;
		tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
		@@ -97,13 +99,14 @@ static void mn10300_cpupic_mask_ack(unsigned int irq)
		#endif /* CONFIG_SMP */
		}

		static void mn10300_cpupic_unmask(unsigned int irq)
		static void mn10300_cpupic_unmask(struct irq_data *d)
		{
		__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE);
		__mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
		}

		static void mn10300_cpupic_unmask_clear(unsigned int irq)
		static void mn10300_cpupic_unmask_clear(struct irq_data *d)
		{
		unsigned int irq = d->irq;
		/* the MN10300 PIC latches its interrupt request bit, even after the
		* device has ceased to assert its interrupt line and the interrupt
		* channel has been disabled in the PIC, so for level-triggered
		@@ -121,7 +124,7 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq)
		} else {
		tmp = GxICR(irq);

		irq_affinity_online[irq] = any_online_cpu(*irq_desc[irq].affinity);
		irq_affinity_online[irq] = any_online_cpu(*d->affinity);
		CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) \| GxICR_ENABLE \| GxICR_DETECT;
		tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
		}
		@@ -134,7 +137,8 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq)

		#ifdef CONFIG_SMP
		static int
		mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
		mn10300_cpupic_setaffinity(struct irq_data d, const struct cpumask mask,
		bool force)
		{
		unsigned long flags;
		int err;
		@@ -142,7 +146,7 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
		flags = arch_local_cli_save();

		/* check irq no */
		switch (irq) {
		switch (d->irq) {
		case TMJCIRQ:
		case RESCHEDULE_IPI:
		case CALL_FUNC_SINGLE_IPI:
		@@ -181,7 +185,7 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
		break;

		default:
		set_bit(irq, irq_affinity_request);
		set_bit(d->irq, irq_affinity_request);
		err = 0;
		break;
		}
		@@ -203,14 +207,14 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
		*/
		static struct irq_chip mn10300_cpu_pic_level = {
		.name = "cpu_l",
		.disable = mn10300_cpupic_mask,
		.enable = mn10300_cpupic_unmask_clear,
		.ack = NULL,
		.mask = mn10300_cpupic_mask,
		.mask_ack = mn10300_cpupic_mask,
		.unmask = mn10300_cpupic_unmask_clear,
		.irq_disable = mn10300_cpupic_mask,
		.irq_enable = mn10300_cpupic_unmask_clear,
		.irq_ack = NULL,
		.irq_mask = mn10300_cpupic_mask,
		.irq_mask_ack = mn10300_cpupic_mask,
		.irq_unmask = mn10300_cpupic_unmask_clear,
		#ifdef CONFIG_SMP
		.set_affinity = mn10300_cpupic_setaffinity,
		.irq_set_affinity = mn10300_cpupic_setaffinity,
		#endif
		};

		@@ -221,14 +225,14 @@ static struct irq_chip mn10300_cpu_pic_level = {
		*/
		static struct irq_chip mn10300_cpu_pic_edge = {
		.name = "cpu_e",
		.disable = mn10300_cpupic_mask,
		.enable = mn10300_cpupic_unmask,
		.ack = mn10300_cpupic_ack,
		.mask = mn10300_cpupic_mask,
		.mask_ack = mn10300_cpupic_mask_ack,
		.unmask = mn10300_cpupic_unmask,
		.irq_disable = mn10300_cpupic_mask,
		.irq_enable = mn10300_cpupic_unmask,
		.irq_ack = mn10300_cpupic_ack,
		.irq_mask = mn10300_cpupic_mask,
		.irq_mask_ack = mn10300_cpupic_mask_ack,
		.irq_unmask = mn10300_cpupic_unmask,
		#ifdef CONFIG_SMP
		.set_affinity = mn10300_cpupic_setaffinity,
		.irq_set_affinity = mn10300_cpupic_setaffinity,
		#endif
		};

		@@ -271,7 +275,7 @@ void __init init_IRQ(void)
		int irq;

		for (irq = 0; irq < NR_IRQS; irq++)
		if (irq_desc[irq].chip == &no_irq_chip)
		if (get_irq_chip(irq) == &no_irq_chip)
		/* due to the PIC latching interrupt requests, even
		* when the IRQ is disabled, IRQ_PENDING is superfluous
		* and we can use handle_level_irq() for edge-triggered