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Commit 12444d5f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2013-10-07' of... 

Merge tag 'drm-intel-fixes-2013-10-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes

Daniel writes:
Just a few important fixes, all cc: stable (I've checked this time around
and made sure they're really there ...). The dpms one is a regression from
the modeset rework and has a good chance to rectify Linus' hdmi issues.

* tag 'drm-intel-fixes-2013-10-07' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: Only apply DPMS to the encoder if enabled
  drm/i915: Mask LPSP to get PSR working even with Power Well in use by audio.
  drm/i915/hsw: Disable L3 caching of atomic memory operations.
  drm/i915: fix rps.vlv_work initialization
parents d0e639c9 c9976dcf

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -3881,6 +3881,9 @@ 
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)





#define HSW_SCRATCH1				0xb038

#define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)



#define HSW_FUSE_STRAP		0x42014

#define HSW_FUSE_STRAP		0x42014

#define  HSW_CDCLK_LIMIT	(1 << 24)

#define  HSW_CDCLK_LIMIT	(1 << 24)
@@ -4728,6 +4731,9 @@ 
#define GEN7_ROW_CHICKEN2_GT2		0xf4f4

#define GEN7_ROW_CHICKEN2_GT2		0xf4f4

#define   DOP_CLOCK_GATING_DISABLE	(1<<0)

#define   DOP_CLOCK_GATING_DISABLE	(1<<0)





#define HSW_ROW_CHICKEN3		0xe49c

#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)



#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)

#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)

#define INTEL_AUDIO_DEVCL		0x808629FB

#define INTEL_AUDIO_DEVCL		0x808629FB

#define INTEL_AUDIO_DEVBLC		0x80862801

#define INTEL_AUDIO_DEVBLC		0x80862801

drivers/gpu/drm/i915/intel_display.c

+2 −6
Original line number Original line Diff line number Diff line
@@ -3941,8 +3941,6 @@ static void intel_connector_check_state(struct intel_connector *connector) 
 * consider. */

 * consider. */

void intel_connector_dpms(struct drm_connector *connector, int mode)

void intel_connector_dpms(struct drm_connector *connector, int mode)

{

{

	struct intel_encoder *encoder = intel_attached_encoder(connector);



	/* All the simple cases only support two dpms states. */

	/* All the simple cases only support two dpms states. */

	if (mode != DRM_MODE_DPMS_ON)

	if (mode != DRM_MODE_DPMS_ON)

		mode = DRM_MODE_DPMS_OFF;

		mode = DRM_MODE_DPMS_OFF;
@@ -3953,10 +3951,8 @@ void intel_connector_dpms(struct drm_connector *connector, int mode) 
	connector->dpms = mode;

	connector->dpms = mode;





	/* Only need to change hw state when actually enabled */

	/* Only need to change hw state when actually enabled */

	if (encoder->base.crtc)

	if (connector->encoder)

		intel_encoder_dpms(encoder, mode);

		intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);

	else

		WARN_ON(encoder->connectors_active != false);





	intel_modeset_check_state(connector->dev);

	intel_modeset_check_state(connector->dev);

}

}

drivers/gpu/drm/i915/intel_dp.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1467,7 +1467,7 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp) 




	/* Avoid continuous PSR exit by masking memup and hpd */

	/* Avoid continuous PSR exit by masking memup and hpd */

	I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |

	I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |

		   EDP_PSR_DEBUG_MASK_HPD);

		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);





	intel_dp->psr_setup_done = true;

	intel_dp->psr_setup_done = true;

}

}

drivers/gpu/drm/i915/intel_pm.c

+7 −2
Original line number Original line Diff line number Diff line
@@ -3864,8 +3864,6 @@ static void valleyview_enable_rps(struct drm_device *dev) 
				      dev_priv->rps.rpe_delay),

				      dev_priv->rps.rpe_delay),

			 dev_priv->rps.rpe_delay);

			 dev_priv->rps.rpe_delay);





	INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);



	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);

	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);





	gen6_enable_rps_interrupts(dev);

	gen6_enable_rps_interrupts(dev);
@@ -4955,6 +4953,11 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);

			GEN7_WA_L3_CHICKEN_MODE);





	/* L3 caching of data atomics doesn't work -- disable it. */

	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);

	I915_WRITE(HSW_ROW_CHICKEN3,

		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));



	/* This is required by WaCatErrorRejectionIssue:hsw */

	/* This is required by WaCatErrorRejectionIssue:hsw */

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
@@ -5681,5 +5684,7 @@ void intel_pm_init(struct drm_device *dev) 




	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,

	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,

			  intel_gen6_powersave_work);

			  intel_gen6_powersave_work);



	INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);

}

}