[media] omap3isp: CCP2/CSI2 receivers

/*

 * ispccp2.h

 *

 * TI OMAP3 ISP - CCP2 module

 *

 * Copyright (C) 2010 Nokia Corporation

 * Copyright (C) 2010 Texas Instruments, Inc.

 *

 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

 *	     Sakari Ailus <sakari.ailus@iki.fi>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA

 * 02110-1301 USA

 */

#ifndef OMAP3_ISP_CCP2_H

#define OMAP3_ISP_CCP2_H

#include <linux/videodev2.h>

struct isp_device;

struct isp_csiphy;

/* Sink and source ccp2 pads */

#define CCP2_PAD_SINK			0

#define CCP2_PAD_SOURCE			1

#define CCP2_PADS_NUM			2

/* CCP2 input media entity */

enum ccp2_input_entity {

	CCP2_INPUT_NONE,

	CCP2_INPUT_SENSOR,

	CCP2_INPUT_MEMORY,

};

/* CCP2 output media entity */

enum ccp2_output_entity {

	CCP2_OUTPUT_NONE,

	CCP2_OUTPUT_CCDC,

	CCP2_OUTPUT_MEMORY,

};

/* Logical channel configuration */

struct isp_interface_lcx_config {

	int crc;

	u32 data_start;

	u32 data_size;

	u32 format;

};

/* Memory channel configuration */

struct isp_interface_mem_config {

	u32 dst_port;

	u32 vsize_count;

	u32 hsize_count;

	u32 src_ofst;

	u32 dst_ofst;

};

/* CCP2 device */

struct isp_ccp2_device {

	struct v4l2_subdev subdev;

	struct v4l2_mbus_framefmt formats[CCP2_PADS_NUM];

	struct media_pad pads[CCP2_PADS_NUM];

	enum ccp2_input_entity input;

	enum ccp2_output_entity output;

	struct isp_interface_lcx_config if_cfg;

	struct isp_interface_mem_config mem_cfg;

	struct isp_video video_in;

	struct isp_csiphy *phy;

	unsigned int error;

	enum isp_pipeline_stream_state state;

	wait_queue_head_t wait;

	atomic_t stopping;

};

/* Function declarations */

int omap3isp_ccp2_init(struct isp_device *isp);

void omap3isp_ccp2_cleanup(struct isp_device *isp);

int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,

			struct v4l2_device *vdev);

void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2);

int omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2);

#endif	/* OMAP3_ISP_CCP2_H */

/*

 * ispcsi2.h

 *

 * TI OMAP3 ISP - CSI2 module

 *

 * Copyright (C) 2010 Nokia Corporation

 * Copyright (C) 2009 Texas Instruments, Inc.

 *

 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

 *	     Sakari Ailus <sakari.ailus@iki.fi>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA

 * 02110-1301 USA

 */

#ifndef OMAP3_ISP_CSI2_H

#define OMAP3_ISP_CSI2_H

#include <linux/types.h>

#include <linux/videodev2.h>

struct isp_csiphy;

/* This is not an exhaustive list */

enum isp_csi2_pix_formats {

	CSI2_PIX_FMT_OTHERS = 0,

	CSI2_PIX_FMT_YUV422_8BIT = 0x1e,

	CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,

	CSI2_PIX_FMT_RAW10_EXP16 = 0xab,

	CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,

	CSI2_PIX_FMT_RAW8 = 0x2a,

	CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,

	CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,

	CSI2_PIX_FMT_RAW8_VP = 0x12a,

	CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,

	CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,

	CSI2_USERDEF_8BIT_DATA1 = 0x40,

};

enum isp_csi2_irqevents {

	OCP_ERR_IRQ = 0x4000,

	SHORT_PACKET_IRQ = 0x2000,

	ECC_CORRECTION_IRQ = 0x1000,

	ECC_NO_CORRECTION_IRQ = 0x800,

	COMPLEXIO2_ERR_IRQ = 0x400,

	COMPLEXIO1_ERR_IRQ = 0x200,

	FIFO_OVF_IRQ = 0x100,

	CONTEXT7 = 0x80,

	CONTEXT6 = 0x40,

	CONTEXT5 = 0x20,

	CONTEXT4 = 0x10,

	CONTEXT3 = 0x8,

	CONTEXT2 = 0x4,

	CONTEXT1 = 0x2,

	CONTEXT0 = 0x1,

};

enum isp_csi2_ctx_irqevents {

	CTX_ECC_CORRECTION = 0x100,

	CTX_LINE_NUMBER = 0x80,

	CTX_FRAME_NUMBER = 0x40,

	CTX_CS = 0x20,

	CTX_LE = 0x8,

	CTX_LS = 0x4,

	CTX_FE = 0x2,

	CTX_FS = 0x1,

};

enum isp_csi2_frame_mode {

	ISP_CSI2_FRAME_IMMEDIATE,

	ISP_CSI2_FRAME_AFTERFEC,

};

#define ISP_CSI2_MAX_CTX_NUM	7

struct isp_csi2_ctx_cfg {

	u8 ctxnum;		/* context number 0 - 7 */

	u8 dpcm_decompress;

	/* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */

	u8 virtual_id;

	u16 format_id;		/* as in CSI2_CTx_CTRL2[9:0] */

	u8 dpcm_predictor;	/* 1: simple, 0: advanced */

	/* Fields in CSI2_CTx_CTRL1/3 - Shadowed */

	u16 alpha;

	u16 data_offset;

	u32 ping_addr;

	u32 pong_addr;

	u8 eof_enabled;

	u8 eol_enabled;

	u8 checksum_enabled;

	u8 enabled;

};

struct isp_csi2_timing_cfg {

	u8 ionum;			/* IO1 or IO2 as in CSI2_TIMING */

	unsigned force_rx_mode:1;

	unsigned stop_state_16x:1;

	unsigned stop_state_4x:1;

	u16 stop_state_counter;

};

struct isp_csi2_ctrl_cfg {

	bool vp_clk_enable;

	bool vp_only_enable;

	u8 vp_out_ctrl;

	enum isp_csi2_frame_mode frame_mode;

	bool ecc_enable;

	bool if_enable;

};

#define CSI2_PAD_SINK		0

#define CSI2_PAD_SOURCE		1

#define CSI2_PADS_NUM		2

#define CSI2_OUTPUT_CCDC	(1 << 0)

#define CSI2_OUTPUT_MEMORY	(1 << 1)

struct isp_csi2_device {

	struct v4l2_subdev subdev;

	struct media_pad pads[CSI2_PADS_NUM];

	struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];

	struct isp_video video_out;

	struct isp_device *isp;

	u8 available;		/* Is the IP present on the silicon? */

	/* mem resources - enums as defined in enum isp_mem_resources */

	u8 regs1;

	u8 regs2;

	u32 output; /* output to CCDC, memory or both? */

	bool dpcm_decompress;

	unsigned int frame_skip;

	bool use_fs_irq;

	struct isp_csiphy *phy;

	struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];

	struct isp_csi2_timing_cfg timing[2];

	struct isp_csi2_ctrl_cfg ctrl;

	enum isp_pipeline_stream_state state;

	wait_queue_head_t wait;

	atomic_t stopping;

};

int omap3isp_csi2_isr(struct isp_csi2_device *csi2);

int omap3isp_csi2_reset(struct isp_csi2_device *csi2);

int omap3isp_csi2_init(struct isp_device *isp);

void omap3isp_csi2_cleanup(struct isp_device *isp);

void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);

int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,

				    struct v4l2_device *vdev);

#endif	/* OMAP3_ISP_CSI2_H */

/*

 * ispcsiphy.c

 *

 * TI OMAP3 ISP - CSI PHY module

 *

 * Copyright (C) 2010 Nokia Corporation

 * Copyright (C) 2009 Texas Instruments, Inc.

 *

 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

 *	     Sakari Ailus <sakari.ailus@iki.fi>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA

 * 02110-1301 USA

 */

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/regulator/consumer.h>

#include "isp.h"

#include "ispreg.h"

#include "ispcsiphy.h"

/*

 * csiphy_lanes_config - Configuration of CSIPHY lanes.

 *

 * Updates HW configuration.

 * Called with phy->mutex taken.

 */

static void csiphy_lanes_config(struct isp_csiphy *phy)

{

	unsigned int i;

	u32 reg;

	reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG);

	for (i = 0; i < phy->num_data_lanes; i++) {

		reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) |

			 ISPCSI2_PHY_CFG_DATA_POSITION_MASK(i + 1));

		reg |= (phy->lanes.data[i].pol <<

			ISPCSI2_PHY_CFG_DATA_POL_SHIFT(i + 1));

		reg |= (phy->lanes.data[i].pos <<

			ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(i + 1));

	}

	reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK |

		 ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK);

	reg |= phy->lanes.clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT;

	reg |= phy->lanes.clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT;

	isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG);

}

/*

 * csiphy_power_autoswitch_enable

 * @enable: Sets or clears the autoswitch function enable flag.

 */

static void csiphy_power_autoswitch_enable(struct isp_csiphy *phy, bool enable)

{

	isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,

			ISPCSI2_PHY_CFG_PWR_AUTO,

			enable ? ISPCSI2_PHY_CFG_PWR_AUTO : 0);

}

/*

 * csiphy_set_power

 * @power: Power state to be set.

 *

 * Returns 0 if successful, or -EBUSY if the retry count is exceeded.

 */

static int csiphy_set_power(struct isp_csiphy *phy, u32 power)

{

	u32 reg;

	u8 retry_count;

	isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,

			ISPCSI2_PHY_CFG_PWR_CMD_MASK, power);

	retry_count = 0;

	do {

		udelay(50);

		reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) &

				    ISPCSI2_PHY_CFG_PWR_STATUS_MASK;

		if (reg != power >> 2)

			retry_count++;

	} while ((reg != power >> 2) && (retry_count < 100));

	if (retry_count == 100) {

		printk(KERN_ERR "CSI2 CIO set power failed!\n");

		return -EBUSY;

	}

	return 0;

}

/*

 * csiphy_dphy_config - Configure CSI2 D-PHY parameters.

 *

 * Called with phy->mutex taken.

 */

static void csiphy_dphy_config(struct isp_csiphy *phy)

{

	u32 reg;

	/* Set up ISPCSIPHY_REG0 */

	reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0);

	reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK |

		 ISPCSIPHY_REG0_THS_SETTLE_MASK);

	reg |= phy->dphy.ths_term << ISPCSIPHY_REG0_THS_TERM_SHIFT;

	reg |= phy->dphy.ths_settle << ISPCSIPHY_REG0_THS_SETTLE_SHIFT;

	isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0);

	/* Set up ISPCSIPHY_REG1 */

	reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1);

	reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK |

		 ISPCSIPHY_REG1_TCLK_MISS_MASK |

		 ISPCSIPHY_REG1_TCLK_SETTLE_MASK);

	reg |= phy->dphy.tclk_term << ISPCSIPHY_REG1_TCLK_TERM_SHIFT;

	reg |= phy->dphy.tclk_miss << ISPCSIPHY_REG1_TCLK_MISS_SHIFT;

	reg |= phy->dphy.tclk_settle << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT;

	isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1);

}

static int csiphy_config(struct isp_csiphy *phy,

			 struct isp_csiphy_dphy_cfg *dphy,

			 struct isp_csiphy_lanes_cfg *lanes)

{

	unsigned int used_lanes = 0;

	unsigned int i;

	/* Clock and data lanes verification */

	for (i = 0; i < phy->num_data_lanes; i++) {

		if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3)

			return -EINVAL;

		if (used_lanes & (1 << lanes->data[i].pos))

			return -EINVAL;

		used_lanes |= 1 << lanes->data[i].pos;

	}

	if (lanes->clk.pol > 1 || lanes->clk.pos > 3)

		return -EINVAL;

	if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))

		return -EINVAL;

	mutex_lock(&phy->mutex);

	phy->dphy = *dphy;

	phy->lanes = *lanes;

	mutex_unlock(&phy->mutex);

	return 0;

}

int omap3isp_csiphy_acquire(struct isp_csiphy *phy)

{

	int rval;

	if (phy->vdd == NULL) {

		dev_err(phy->isp->dev, "Power regulator for CSI PHY not "

			"available\n");

		return -ENODEV;

	}

	mutex_lock(&phy->mutex);

	rval = regulator_enable(phy->vdd);

	if (rval < 0)

		goto done;

	omap3isp_csi2_reset(phy->csi2);

	csiphy_dphy_config(phy);

	csiphy_lanes_config(phy);

	rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);

	if (rval) {

		regulator_disable(phy->vdd);

		goto done;

	}

	csiphy_power_autoswitch_enable(phy, true);

	phy->phy_in_use = 1;

done:

	mutex_unlock(&phy->mutex);

	return rval;

}

void omap3isp_csiphy_release(struct isp_csiphy *phy)

{

	mutex_lock(&phy->mutex);

	if (phy->phy_in_use) {

		csiphy_power_autoswitch_enable(phy, false);

		csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);

		regulator_disable(phy->vdd);

		phy->phy_in_use = 0;

	}

	mutex_unlock(&phy->mutex);

}

/*

 * omap3isp_csiphy_init - Initialize the CSI PHY frontends

 */

int omap3isp_csiphy_init(struct isp_device *isp)

{

	struct isp_csiphy *phy1 = &isp->isp_csiphy1;

	struct isp_csiphy *phy2 = &isp->isp_csiphy2;

	isp->platform_cb.csiphy_config = csiphy_config;

	phy2->isp = isp;

	phy2->csi2 = &isp->isp_csi2a;

	phy2->num_data_lanes = ISP_CSIPHY2_NUM_DATA_LANES;

	phy2->cfg_regs = OMAP3_ISP_IOMEM_CSI2A_REGS1;

	phy2->phy_regs = OMAP3_ISP_IOMEM_CSIPHY2;

	mutex_init(&phy2->mutex);

	if (isp->revision == ISP_REVISION_15_0) {

		phy1->isp = isp;

		phy1->csi2 = &isp->isp_csi2c;

		phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES;

		phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1;

		phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1;

		mutex_init(&phy1->mutex);

	}

	return 0;

}