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Commit 11ff376f authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

clk: rockchip: fix rk3066 pll status register location 



The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9c030ea7

drivers/clk/rockchip/clk-rk3188.c

+7 −3
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <dt-bindings/clock/rk3188-cru-common.h>

#include "clk.h"



#define RK3066_GRF_SOC_STATUS	0x15c

#define RK3188_GRF_SOC_STATUS	0xac



enum rk3188_plls {
@@ -629,9 +630,6 @@ static void __init rk3188_common_clk_init(struct device_node *np) 
		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_plls(rk3188_pll_clks,

				   ARRAY_SIZE(rk3188_pll_clks),

				   RK3188_GRF_SOC_STATUS);

	rockchip_clk_register_branches(common_clk_branches,

				  ARRAY_SIZE(common_clk_branches));

	rockchip_clk_protect_critical(rk3188_critical_clocks,
@@ -644,6 +642,9 @@ static void __init rk3188_common_clk_init(struct device_node *np) 
static void __init rk3066a_clk_init(struct device_node *np)

{

	rk3188_common_clk_init(np);

	rockchip_clk_register_plls(rk3188_pll_clks,

				   ARRAY_SIZE(rk3188_pll_clks),

				   RK3066_GRF_SOC_STATUS);

	rockchip_clk_register_branches(rk3066a_clk_branches,

				  ARRAY_SIZE(rk3066a_clk_branches));

}
@@ -652,6 +653,9 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); 
static void __init rk3188a_clk_init(struct device_node *np)

{

	rk3188_common_clk_init(np);

	rockchip_clk_register_plls(rk3188_pll_clks,

				   ARRAY_SIZE(rk3188_pll_clks),

				   RK3188_GRF_SOC_STATUS);

	rockchip_clk_register_branches(rk3188_clk_branches,

				  ARRAY_SIZE(rk3188_clk_branches));

}