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Commit 11d938d4 authored by Rostislav Lisovy's avatar Rostislav Lisovy Committed by Tony Lindgren
Browse files

ARM: dts: am335x: Add DTS for ChiliSOM module 



Since this is a SOM (System on Module) that will be part
of another embedded board (and can't really exist on its own)
define it as a "dtsi" that will be included in the Device tree
describing the whole system later on.

Hardware specification:
* AM335x SoC
* up to 512 MB RAM
* NAND Flash (8x interface, cs0)
* UART0
* PMIC
* I2C0 (for PMIC)
* 1x Ethernet MAC

Signed-off-by: default avatarRostislav Lisovy <lisovy@jablotron.cz>
[tony@atomide.com: updated nand io size to be just 4]
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 1b3a62ae

arch/arm/boot/dts/am335x-chilisom.dtsi

0 → 100644
+239 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/

 * Author: Rostislav Lisovy <lisovy@jablotron.cz>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include "am33xx.dtsi"



/ {

	model = "Grinn AM335x ChiliSOM";

	compatible = "grinn,am335x-chilisom", "ti,am33xx";



	cpus {

		cpu@0 {

			cpu0-supply = <&dcdc2_reg>;

		};

	};



	memory {

		device_type = "memory";

		reg = <0x80000000 0x20000000>; /* 512 MB */

	};

};



&am33xx_pinmux {

	pinctrl-names = "default";



	i2c0_pins: pinmux_i2c0_pins {

		pinctrl-single,pins = <

			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */

			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */

		>;

	};



	uart0_pins: pinmux_uart0_pins {

		pinctrl-single,pins = <

			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */

			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */

		>;

	};



	cpsw_default: cpsw_default {

		pinctrl-single,pins = <

			/* Slave 1 */

			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */

			0x110 (PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */

			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */

			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */

			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */

			0x13c (PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */

			0x140 (PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */

			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_ref_clk.rmii_ref_clk */

		>;

	};



	cpsw_sleep: cpsw_sleep {

		pinctrl-single,pins = <

			/* Slave 1 reset value */

			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)

		>;

	};



	davinci_mdio_default: davinci_mdio_default {

		pinctrl-single,pins = <

			/* mdio_data.mdio_data */

			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)

			/* mdio_clk.mdio_clk */

			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)

		>;

	};



	davinci_mdio_sleep: davinci_mdio_sleep {

		pinctrl-single,pins = <

			/* MDIO reset value */

			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)

			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)

		>;

	};



	nandflash_pins: nandflash_pins {

		pinctrl-single,pins = <

			0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */

			0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */

			0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */

			0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */

			0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */

			0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */

			0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */

			0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */



			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */

			0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_csn0.gpmc_csn0 */

			0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_advn_ale.gpmc_advn_ale */

			0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_oen_ren.gpmc_oen_ren */

			0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_wen.gpmc_wen */

			0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_be0n_cle.gpmc_be0n_cle */

		>;

	};

};



&uart0 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart0_pins>;



	status = "okay";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_pins>;



	status = "okay";

	clock-frequency = <400000>;



	tps: tps@24 {

		reg = <0x24>;

	};



};



/include/ "tps65217.dtsi"



&tps {

	regulators {

		dcdc1_reg: regulator@0 {

			regulator-name = "vdds_dpr";

			regulator-always-on;

		};



		dcdc2_reg: regulator@1 {

			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */

			regulator-name = "vdd_mpu";

			regulator-min-microvolt = <925000>;

			regulator-max-microvolt = <1325000>;

			regulator-boot-on;

			regulator-always-on;

		};



		dcdc3_reg: regulator@2 {

			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */

			regulator-name = "vdd_core";

			regulator-min-microvolt = <925000>;

			regulator-max-microvolt = <1150000>;

			regulator-boot-on;

			regulator-always-on;

		};



		ldo1_reg: regulator@3 {

			regulator-name = "vio,vrtc,vdds";

			regulator-boot-on;

			regulator-always-on;

		};



		ldo2_reg: regulator@4 {

			regulator-name = "vdd_3v3aux";

			regulator-boot-on;

			regulator-always-on;

		};



		ldo3_reg: regulator@5 {

			regulator-name = "vdd_1v8";

			regulator-boot-on;

			regulator-always-on;

		};



		ldo4_reg: regulator@6 {

			regulator-name = "vdd_3v3d";

			regulator-boot-on;

			regulator-always-on;

		};

	};

};



/* Ethernet MAC */

&mac {

	slaves = <1>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&cpsw_default>;

	pinctrl-1 = <&cpsw_sleep>;

	status = "okay";

};



&davinci_mdio {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&davinci_mdio_default>;

	pinctrl-1 = <&davinci_mdio_sleep>;

	status = "okay";

};



/* NAND Flash */

&elm {

	status = "okay";

};



&gpmc {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&nandflash_pins>;

	ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */

	nand@0,0 {

		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */

		ti,nand-ecc-opt = "bch8";

		ti,elm-id = <&elm>;

		nand-bus-width = <8>;

		gpmc,device-width = <1>;

		gpmc,sync-clk-ps = <0>;

		gpmc,cs-on-ns = <0>;

		gpmc,cs-rd-off-ns = <44>;

		gpmc,cs-wr-off-ns = <44>;

		gpmc,adv-on-ns = <6>;

		gpmc,adv-rd-off-ns = <34>;

		gpmc,adv-wr-off-ns = <44>;

		gpmc,we-on-ns = <0>;

		gpmc,we-off-ns = <40>;

		gpmc,oe-on-ns = <0>;

		gpmc,oe-off-ns = <54>;

		gpmc,access-ns = <64>;

		gpmc,rd-cycle-ns = <82>;

		gpmc,wr-cycle-ns = <82>;

		gpmc,wait-on-read = "true";

		gpmc,wait-on-write = "true";

		gpmc,bus-turnaround-ns = <0>;

		gpmc,cycle2cycle-delay-ns = <0>;

		gpmc,clk-activation-ns = <0>;

		gpmc,wait-monitoring-ns = <0>;

		gpmc,wr-access-ns = <40>;

		gpmc,wr-data-mux-bus-ns = <0>;

	};

};