Merge tag 'renesas-dt3-for-v3.14' of...

* Renesas CPG DIV6 Clock

The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse

Generator (CPG). They clock input is divided by a configurable factor from 1

to 64.

Required Properties:

  - compatible: Must be one of the following

    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks

    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks

    - "renesas,cpg-div6-clock" for generic DIV6 clocks

  - reg: Base address and length of the memory resource used by the DIV6 clock

  - clocks: Reference to the parent clock

  - #clock-cells: Must be 0

  - clock-output-names: The name of the clock as a free-form string

Example

-------

	sd2_clk: sd2_clk@e6150078 {

		compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";

		reg = <0 0xe6150078 0 4>;

		clocks = <&pll1_div2_clk>;

		#clock-cells = <0>;

		clock-output-names = "sd2";

	};

* Renesas CPG Module Stop (MSTP) Clocks

The CPG can gate SoC device clocks. The gates are organized in groups of up to

32 gates.

This device tree binding describes a single 32 gate clocks group per node.

Clocks are referenced by user nodes by the MSTP node phandle and the clock

index in the group, from 0 to 31.

Required Properties:

  - compatible: Must be one of the following

    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks

    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks

    - "renesas,cpg-mstp-clock" for generic MSTP gate clocks

  - reg: Base address and length of the I/O mapped registers used by the MSTP

    clocks. The first register is the clock control register and is mandatory.

    The second register is the clock status register and is optional when not

    implemented in hardware.

  - clocks: Reference to the parent clocks, one per output clock. The parents

    must appear in the same order as the output clocks.

  - #clock-cells: Must be 1

  - clock-output-names: The name of the clocks as free-form strings

  - renesas,indices: Indices of the gate clocks into the group (0 to 31)

The clocks, clock-output-names and renesas,indices properties contain one

entry per gate clock. The MSTP groups are sparsely populated. Unimplemented

gate clocks must not be declared.

Example

-------

	#include <dt-bindings/clock/r8a7790-clock.h>

	mstp3_clks: mstp3_clks@e615013c {

		compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

		reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

		clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,

			 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,

			 <&mmc0_clk>;

		#clock-cells = <1>;

		clock-output-names =

			"tpu0", "mmcif1", "sdhi3", "sdhi2",

			 "sdhi1", "sdhi0", "mmcif0";

		renesas,clock-indices = <

			R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

			R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0

			R8A7790_CLK_MMCIF0

		>;

	};

* Renesas R-Car Gen2 Clock Pulse Generator (CPG)

The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs

and several fixed ratio dividers.

Required Properties:

  - compatible: Must be one of

    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG

    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG

    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG

  - reg: Base address and length of the memory resource used by the CPG

  - clocks: Reference to the parent clock

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"

Example

-------

	cpg_clocks: cpg_clocks@e6150000 {

		compatible = "renesas,r8a7790-cpg-clocks",

			     "renesas,rcar-gen2-cpg-clocks";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk>;

		#clock-cells = <1>;

		clock-output-names = "main", "pll0, "pll1", "pll3",

				     "lb", "qspi", "sdh", "sd0", "sd1", "z";

	};

* Freescale IMX25 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.

CONFIG bits definition:

PAD_CTL_HYS			(1 << 8)

PAD_CTL_PKE			(1 << 7)

PAD_CTL_PUE			(1 << 6)

PAD_CTL_PUS_100K_DOWN		(0 << 4)

PAD_CTL_PUS_47K_UP		(1 << 4)

PAD_CTL_PUS_100K_UP		(2 << 4)

PAD_CTL_PUS_22K_UP		(3 << 4)

PAD_CTL_ODE_CMOS		(0 << 3)

PAD_CTL_ODE_OPENDRAIN		(1 << 3)

PAD_CTL_DSE_NOMINAL		(0 << 1)

PAD_CTL_DSE_HIGH		(1 << 1)

PAD_CTL_DSE_MAX			(2 << 1)

PAD_CTL_SRE_FAST		(1 << 0)

PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx25-pinfunc.h in device tree source folder for all available

imx25 PIN_FUNC_ID.

  CONFIG can be 0 or 1, meaning Pullup disable/enable.

The iomux controller has gpio child nodes which are embedded in the iomux

control registers. They have to be defined as child nodes of the iomux device

node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"

properties for the iomux device node are required.

Example:

iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	gpio1: gpio@10015000 {

		...

	};

	...

	uart {

		pinctrl_uart1: uart-1 {

iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	gpio1: gpio@10015000 {

		...

	};

	...

	uart {

		pinctrl_uart1: uart-1 {