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Commit 1180e206 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Jani Nikula
Browse files

drm/i915: properly reenable gen8 pipe IRQs 

We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.

This should fix a bunch of IGT tests.

There are a few more things we could improve on this code, but this
should be the minimal fix to unblock us.

v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)

Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640


Testcase: igt/*
Cc: stable@vger.kernel.org
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 2e541625

drivers/gpu/drm/i915/i915_irq.c

+3 −2
Original line number Diff line number Diff line
@@ -3458,12 +3458,13 @@ static void gen8_irq_reset(struct drm_device *dev) 
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)

{

	unsigned long irqflags;

	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;



	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],

			  ~dev_priv->de_irq_mask[PIPE_B]);

			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);

	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],

			  ~dev_priv->de_irq_mask[PIPE_C]);

			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

}