Commit 117e5e9c authored Sep 30, 2016 by Srinivas Ramana Committed by Russell King Oct 02, 2016

ARM: 8618/1: decompressor: reset ttbcr fields to use TTBR0 on ARMv7



If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU, it is required to clear the TTBCR.PD0
field to use TTBR0 for translation table walks.

The commit dbece458 ("ARM: 7501/1: decompressor:
reset ttbcr for VMSA ARMv7 cores") does the reset of TTBCR.N, but
doesn't consider all the bits for the size of TTBCR.N.

Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
indicate the use of TTBR0 and the correct base address width.

Fixes: dbece458 ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent d248220f

arch/arm/boot/compressed/head.S

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -779,7 +779,7 @@ __armv7_mmu_cache_on:
	orrne r0, r0, #1 @ MMU enabled		orrne r0, r0, #1 @ MMU enabled
	movne r1, #0xfffffffd @ domain 0 = client		movne r1, #0xfffffffd @ domain 0 = client
	bic r6, r6, #1 << 31 @ 32-bit translation system		bic r6, r6, #1 << 31 @ 32-bit translation system
	bic r6, r6, #3 << 0 @ use only ttbr0		bic r6, r6, #(7 << 0) \| (1 << 4) @ use only ttbr0
	mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer		mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
	mcrne p15, 0, r1, c3, c0, 0 @ load domain access control		mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
	mcrne p15, 0, r6, c2, c0, 2 @ load ttb control		mcrne p15, 0, r6, c2, c0, 2 @ load ttb control