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Commit 10cc3529 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Allow hardwiring of the CPU type to a single type for optimization. 



This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent aeffdbba

arch/mips/dec/ecc-berr.c

+1 −1
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void) 
	 */

	*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |

	       KN03_MCR_CORRECT;

	if (current_cpu_data.cputype == CPU_R4400SC)

	if (current_cpu_type() == CPU_R4400SC)

		*mbcs |= KN4K_MB_CSR_EE;

	fast_iob();

}

arch/mips/dec/kn02xa-berr.c

+1 −1
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void) 
	volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);



        /* For KN04 we need to make sure EE (?) is enabled in the MB.  */

        if (current_cpu_data.cputype == CPU_R4000SC)

        if (current_cpu_type() == CPU_R4000SC)

		*mbcs |= KN4K_MB_CSR_EE;

	fast_iob();

arch/mips/dec/prom/init.c

+4 −4
Original line number Diff line number Diff line
@@ -108,8 +108,8 @@ void __init prom_init(void) 


	/* Were we compiled with the right CPU option? */

#if defined(CONFIG_CPU_R3000)

	if ((current_cpu_data.cputype == CPU_R4000SC) ||

	    (current_cpu_data.cputype == CPU_R4400SC)) {

	if ((current_cpu_type() == CPU_R4000SC) ||

	    (current_cpu_type() == CPU_R4400SC)) {

		static char r4k_msg[] __initdata =

			"Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";

		printk(cpu_msg);
@@ -119,8 +119,8 @@ void __init prom_init(void) 
#endif



#if defined(CONFIG_CPU_R4X00)

	if ((current_cpu_data.cputype == CPU_R3000) ||

	    (current_cpu_data.cputype == CPU_R3000A)) {

	if ((current_cpu_type() == CPU_R3000) ||

	    (current_cpu_type() == CPU_R3000A)) {

		static char r3k_msg[] __initdata =

			"Please recompile with \"CONFIG_CPU_R3000 = y\".\n";

		printk(cpu_msg);

arch/mips/kernel/traps.c

+3 −3
Original line number Diff line number Diff line
@@ -954,7 +954,7 @@ asmlinkage void do_reserved(struct pt_regs *regs) 
 */

static inline void parity_protection_init(void)

{

	switch (current_cpu_data.cputype) {

	switch (current_cpu_type()) {

	case CPU_24K:

	case CPU_34K:

	case CPU_5KC:
@@ -1549,8 +1549,8 @@ void __init trap_init(void) 
	set_except_vector(12, handle_ov);

	set_except_vector(13, handle_tr);



	if (current_cpu_data.cputype == CPU_R6000 ||

	    current_cpu_data.cputype == CPU_R6000A) {

	if (current_cpu_type() == CPU_R6000 ||

	    current_cpu_type() == CPU_R6000A) {

		/*

		 * The R6000 is the only R-series CPU that features a machine

		 * check exception (similar to the R4000 cache error) and

arch/mips/mm/c-r4k.c

+6 −6
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args) 
	r4k_blast_dcache();

	r4k_blast_icache();



	switch (current_cpu_data.cputype) {

	switch (current_cpu_type()) {

	case CPU_R4000SC:

	case CPU_R4000MC:

	case CPU_R4400SC:
@@ -377,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args) 
	 * R4000SC and R4400SC indexed S-cache ops also invalidate primary

	 * caches, so we can bail out early.

	 */

	if (current_cpu_data.cputype == CPU_R4000SC ||

	    current_cpu_data.cputype == CPU_R4000MC ||

	    current_cpu_data.cputype == CPU_R4400SC ||

	    current_cpu_data.cputype == CPU_R4400MC) {

	if (current_cpu_type() == CPU_R4000SC ||

	    current_cpu_type() == CPU_R4000MC ||

	    current_cpu_type() == CPU_R4400SC ||

	    current_cpu_type() == CPU_R4400MC) {

		r4k_blast_scache();

		return;

	}
@@ -1197,7 +1197,7 @@ static void __init coherency_setup(void) 
	 * this bit and; some wire it to zero, others like Toshiba had the

	 * silly idea of putting something else there ...

	 */

	switch (current_cpu_data.cputype) {

	switch (current_cpu_type()) {

	case CPU_R4000PC:

	case CPU_R4000SC:

	case CPU_R4000MC: