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Commit 1091bfa2 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: Add P6600 cases to CPU switch statements 



Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Petri Gynther <pgynther@google.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12343/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5cd0d5be

arch/mips/include/asm/cpu-type.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -79,6 +79,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) 




#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6

#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6

	case CPU_I6400:

	case CPU_I6400:

	case CPU_P6600:

#endif

#endif





#ifdef CONFIG_SYS_HAS_CPU_R3000

#ifdef CONFIG_SYS_HAS_CPU_R3000

arch/mips/kernel/cpu-probe.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -539,6 +539,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) 
	switch (c->cputype) {

	switch (c->cputype) {

	case CPU_PROAPTIV:

	case CPU_PROAPTIV:

	case CPU_P5600:

	case CPU_P5600:

	case CPU_P6600:

		/* proAptiv & related cores use Config6 to enable the FTLB */

		/* proAptiv & related cores use Config6 to enable the FTLB */

		config = read_c0_config6();

		config = read_c0_config6();

		/* Clear the old probability value */

		/* Clear the old probability value */

arch/mips/kernel/perf_event_mipsxx.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 
#endif

#endif

		break;

		break;

	case CPU_P5600:

	case CPU_P5600:

	case CPU_P6600:

	case CPU_I6400:

	case CPU_I6400:

		/* 8-bit event numbers */

		/* 8-bit event numbers */

		raw_id = config & 0x1ff;

		raw_id = config & 0x1ff;
@@ -1718,6 +1719,11 @@ init_hw_perf_events(void) 
		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		break;

		break;

	case CPU_P6600:

		mipspmu.name = "mips/P6600";

		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		break;

	case CPU_I6400:

	case CPU_I6400:

		mipspmu.name = "mips/I6400";

		mipspmu.name = "mips/I6400";

		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.general_event_map = &mipsxxcore_event_map2;

arch/mips/kernel/spram.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -210,6 +210,7 @@ void spram_config(void) 
	case CPU_P5600:

	case CPU_P5600:

	case CPU_QEMU_GENERIC:

	case CPU_QEMU_GENERIC:

	case CPU_I6400:

	case CPU_I6400:

	case CPU_P6600:

		config0 = read_c0_config();

		config0 = read_c0_config();

		/* FIXME: addresses are Malta specific */

		/* FIXME: addresses are Malta specific */

		if (config0 & (1<<24)) {

		if (config0 & (1<<24)) {

arch/mips/kernel/traps.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1644,6 +1644,7 @@ static inline void parity_protection_init(void) 
	case CPU_P5600:

	case CPU_P5600:

	case CPU_QEMU_GENERIC:

	case CPU_QEMU_GENERIC:

	case CPU_I6400:

	case CPU_I6400:

	case CPU_P6600:

		{

		{

#define ERRCTL_PE	0x80000000

#define ERRCTL_PE	0x80000000

#define ERRCTL_L2P	0x00800000

#define ERRCTL_L2P	0x00800000