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Commit 108f303f authored by Robert Jarzmik's avatar Robert Jarzmik Committed by Mike Turquette
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arm: pxa: add clock pll selection bits



Add missing bits for CCCR and CCSR :
 - CPLL and PPLL selection, either full speed or 13MHz
 - CPSR masks

Signed-off-by: default avatarRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 53f3394a
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+10 −0
Original line number Diff line number Diff line
@@ -143,6 +143,16 @@
#define CCCR_M_MASK	0x0060	/* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK	0x001f	/* Crystal Frequency to Memory Frequency Multiplier */

#define CCCR_CPDIS_BIT	(31)
#define CCCR_PPDIS_BIT	(30)
#define CCCR_LCD_26_BIT	(27)
#define CCCR_A_BIT	(25)

#define CCSR_N2_MASK	CCCR_N_MASK
#define CCSR_M_MASK	CCCR_M_MASK
#define CCSR_L_MASK	CCCR_L_MASK
#define CCSR_N2_SHIFT	7

#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
#define CKEN_CAMERA	(24)	/* Camera Interface Clock Enable */
#define CKEN_SSP1	(23)	/* SSP1 Unit Clock Enable */