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Commit 106b506c authored by Paul Mackerras's avatar Paul Mackerras Committed by Ingo Molnar
Browse files

perf_counter: powerpc: Implement generalized cache events for POWER processors 



This adds tables of event codes for the generalized cache events for
all the currently supported powerpc processors: POWER{4,5,5+,6,7} and
PPC970*, plus powerpc-specific code to use these tables when a
generalized cache event is requested.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <18992.36430.933526.742969@drongo.ozlabs.ibm.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 4da52960

arch/powerpc/include/asm/perf_counter.h

+3 −0
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ struct power_pmu { 
	u32	flags;

	int	n_generic;

	int	*generic_events;

	int	(*cache_events)[PERF_COUNT_HW_CACHE_MAX]

			       [PERF_COUNT_HW_CACHE_OP_MAX]

			       [PERF_COUNT_HW_CACHE_RESULT_MAX];

};



extern struct power_pmu *ppmu;

arch/powerpc/kernel/perf_counter.c

+40 −2
Original line number Diff line number Diff line
@@ -856,6 +856,36 @@ static void hw_perf_counter_destroy(struct perf_counter *counter) 
	}

}



/*

 * Translate a generic cache event config to a raw event code.

 */

static int hw_perf_cache_event(u64 config, u64 *eventp)

{

	unsigned long type, op, result;

	int ev;



	if (!ppmu->cache_events)

		return -EINVAL;



	/* unpack config */

	type = config & 0xff;

	op = (config >> 8) & 0xff;

	result = (config >> 16) & 0xff;



	if (type >= PERF_COUNT_HW_CACHE_MAX ||

	    op >= PERF_COUNT_HW_CACHE_OP_MAX ||

	    result >= PERF_COUNT_HW_CACHE_RESULT_MAX)

		return -EINVAL;



	ev = (*ppmu->cache_events)[type][op][result];

	if (ev == 0)

		return -EOPNOTSUPP;

	if (ev == -1)

		return -EINVAL;

	*eventp = ev;

	return 0;

}



const struct pmu *hw_perf_counter_init(struct perf_counter *counter)

{

	u64 ev;
@@ -868,13 +898,21 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) 


	if (!ppmu)

		return ERR_PTR(-ENXIO);

	if (counter->attr.type != PERF_TYPE_RAW) {

	switch (counter->attr.type) {

	case PERF_TYPE_HARDWARE:

		ev = counter->attr.config;

		if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)

			return ERR_PTR(-EOPNOTSUPP);

		ev = ppmu->generic_events[ev];

	} else {

		break;

	case PERF_TYPE_HW_CACHE:

		err = hw_perf_cache_event(counter->attr.config, &ev);

		if (err)

			return ERR_PTR(err);

		break;

	case PERF_TYPE_RAW:

		ev = counter->attr.config;

		break;

	}

	counter->hw.config_base = ev;

	counter->hw.idx = 0;

arch/powerpc/kernel/power4-pmu.c

+41 −0
Original line number Diff line number Diff line
@@ -543,6 +543,46 @@ static int p4_generic_events[] = { 
	[PERF_COUNT_BRANCH_MISSES] = 0x331,		/* PM_BR_MPRED_CR */

};



#define C(x)	PERF_COUNT_HW_CACHE_##x



/*

 * Table of generalized cache-related events.

 * 0 means not supported, -1 means nonsensical, other values

 * are event codes.

 */

static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x8c10,		0x3c10	},

		[C(OP_WRITE)] = {	0x7c10,		0xc13	},

		[C(OP_PREFETCH)] = {	0xc35,		0	},

	},

	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0	},

		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	0,		0	},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0	},

		[C(OP_WRITE)] = {	0,		0	},

		[C(OP_PREFETCH)] = {	0xc34,		0	},

	},

	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x904	},

		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	-1,		-1	},

	},

	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x900	},

		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	-1,		-1	},

	},

	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x330,		0x331	},

		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	-1,		-1	},

	},

};



struct power_pmu power4_pmu = {

	.n_counter = 8,

	.max_alternatives = 5,
@@ -554,4 +594,5 @@ struct power_pmu power4_pmu = { 
	.disable_pmc = p4_disable_pmc,

	.n_generic = ARRAY_SIZE(p4_generic_events),

	.generic_events = p4_generic_events,

	.cache_events = &power4_cache_events,

};

arch/powerpc/kernel/power5+-pmu.c

+43 −2
Original line number Diff line number Diff line
@@ -614,6 +614,46 @@ static int power5p_generic_events[] = { 
	[PERF_COUNT_BRANCH_MISSES] = 0x230e5,		/* BR_MPRED_CR */

};



#define C(x)	PERF_COUNT_HW_CACHE_##x



/*

 * Table of generalized cache-related events.

 * 0 means not supported, -1 means nonsensical, other values

 * are event codes.

 */

static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x1c10a8,	0x3c1088	},

		[C(OP_WRITE)] = {	0x2c10a8,	0xc10c3		},

		[C(OP_PREFETCH)] = {	0xc70e7,	-1		},

	},

	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	0,		0		},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0		},

		[C(OP_WRITE)] = {	0,		0		},

		[C(OP_PREFETCH)] = {	0xc50c3,	0		},

	},

	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0xc20e4,	0x800c4		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x800c0		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x230e4,	0x230e5		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

};



struct power_pmu power5p_pmu = {

	.n_counter = 6,

	.max_alternatives = MAX_ALT,
@@ -623,8 +663,9 @@ struct power_pmu power5p_pmu = { 
	.get_constraint = power5p_get_constraint,

	.get_alternatives = power5p_get_alternatives,

	.disable_pmc = power5p_disable_pmc,

	.limited_pmc_event = power5p_limited_pmc_event,

	.flags = PPMU_LIMITED_PMC5_6,

	.n_generic = ARRAY_SIZE(power5p_generic_events),

	.generic_events = power5p_generic_events,

	.flags = PPMU_LIMITED_PMC5_6,

	.limited_pmc_event = power5p_limited_pmc_event,

	.cache_events = &power5p_cache_events,

};

arch/powerpc/kernel/power5-pmu.c

+41 −0
Original line number Diff line number Diff line
@@ -556,6 +556,46 @@ static int power5_generic_events[] = { 
	[PERF_COUNT_BRANCH_MISSES] = 0x230e5,		/* BR_MPRED_CR */

};



#define C(x)	PERF_COUNT_HW_CACHE_##x



/*

 * Table of generalized cache-related events.

 * 0 means not supported, -1 means nonsensical, other values

 * are event codes.

 */

static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {

	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x4c1090,	0x3c1088	},

		[C(OP_WRITE)] = {	0x3c1090,	0xc10c3		},

		[C(OP_PREFETCH)] = {	0xc70e7,	0		},

	},

	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	0,		0		},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x3c309b	},

		[C(OP_WRITE)] = {	0,		0		},

		[C(OP_PREFETCH)] = {	0xc50c3,	0		},

	},

	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x2c4090,	0x800c4		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x800c0		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x230e4,	0x230e5		},

		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	-1,		-1		},

	},

};



struct power_pmu power5_pmu = {

	.n_counter = 6,

	.max_alternatives = MAX_ALT,
@@ -567,4 +607,5 @@ struct power_pmu power5_pmu = { 
	.disable_pmc = power5_disable_pmc,

	.n_generic = ARRAY_SIZE(power5_generic_events),

	.generic_events = power5_generic_events,

	.cache_events = &power5_cache_events,

};