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Commit 0f374561 authored by Haojian Zhuang's avatar Haojian Zhuang
Browse files

irqchip: mmp: support irqchip 



Support IRQCHIP & CONFIG_MULTI_IRQ_HANDLER in irq-mmp driver.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: default avatarDaniel Drake <dsd@laptop.org>
parent c052d13c

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -557,6 +557,7 @@ config ARCH_MMP 
	select GENERIC_CLOCKEVENTS

	select GPIO_PXA

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER

	select NEED_MACH_GPIO_H

	select PINCTRL

	select PLAT_PXA

arch/arm/mach-mmp/include/mach/entry-macro.S

deleted100644 → 0
+0 −26
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-mmp/include/mach/entry-macro.S

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <asm/irq.h>

#include <mach/regs-icu.h>



	.macro	get_irqnr_preamble, base, tmp

	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID

	and	\tmp, \tmp, #0xff00

	cmp	\tmp, #0x5800

	ldr	\base, =mmp_icu_base

	ldr	\base, [\base, #0]

	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register

	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register

	.endm



	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp

	ldr	\tmp, [\base, #0]

	and	\irqnr, \tmp, #0x3f

	tst	\tmp, #(1 << 6)

	.endm

arch/arm/mach-mmp/mmp-dt.c

+1 −7
Original line number Diff line number Diff line
@@ -9,17 +9,13 @@ 
 *  publishhed by the Free Software Foundation.

 */



#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/of_irq.h>

#include <linux/irqchip.h>

#include <linux/of_platform.h>

#include <asm/mach/arch.h>

#include <asm/mach/time.h>

#include <mach/irqs.h>



#include "common.h"



extern void __init mmp_dt_irq_init(void);

extern void __init mmp_dt_init_timer(void);



static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = { 


DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")

	.map_io		= mmp_map_io,

	.init_irq	= mmp_dt_irq_init,

	.init_time	= mmp_dt_init_timer,

	.init_machine	= pxa168_dt_init,

	.dt_compat	= mmp_dt_board_compat,
@@ -72,7 +67,6 @@ MACHINE_END 


DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")

	.map_io		= mmp_map_io,

	.init_irq	= mmp_dt_irq_init,

	.init_time	= mmp_dt_init_timer,

	.init_machine	= pxa910_dt_init,

	.dt_compat	= mmp_dt_board_compat,

arch/arm/mach-mmp/mmp2-dt.c

+1 −7
Original line number Diff line number Diff line
@@ -10,18 +10,13 @@ 
 */



#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/of_irq.h>

#include <linux/irqchip.h>

#include <linux/of_platform.h>

#include <asm/mach/arch.h>

#include <asm/mach/time.h>

#include <mach/irqs.h>

#include <mach/regs-apbc.h>



#include "common.h"



extern void __init mmp_dt_irq_init(void);

extern void __init mmp_dt_init_timer(void);



static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = { 


DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")

	.map_io		= mmp_map_io,

	.init_irq	= mmp_dt_irq_init,

	.init_time	= mmp_dt_init_timer,

	.init_machine	= mmp2_dt_init,

	.dt_compat	= mmp2_dt_board_compat,

drivers/irqchip/irq-mmp.c

+165 −115
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ 
#include <linux/of_address.h>

#include <linux/of_irq.h>



#include <asm/exception.h>

#include <asm/mach/irq.h>



#include <mach/irqs.h>



#ifdef CONFIG_CPU_MMP2
@@ -30,8 +33,17 @@ 
#include <mach/pm-pxa910.h>

#endif



#include "irqchip.h"



#define MAX_ICU_NR		16



#define PJ1_INT_SEL		0x10c

#define PJ4_INT_SEL		0x104



/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */

#define SEL_INT_PENDING		(1 << 6)

#define SEL_INT_NUM_MASK	0x3f



struct icu_chip_data {

	int			nr_irqs;

	unsigned int		virq_base;
@@ -52,7 +64,7 @@ struct mmp_intc_conf { 
	unsigned int	conf_mask;

};



void __iomem *mmp_icu_base;

static void __iomem *mmp_icu_base;

static struct icu_chip_data icu_data[MAX_ICU_NR];

static int max_icu_nr;
@@ -191,6 +203,32 @@ static struct mmp_intc_conf mmp2_conf = { 
	.conf_mask	= 0x7f,

};



static asmlinkage void __exception_irq_entry

mmp_handle_irq(struct pt_regs *regs)

{

	int irq, hwirq;



	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);

	if (!(hwirq & SEL_INT_PENDING))

		return;

	hwirq &= SEL_INT_NUM_MASK;

	irq = irq_find_mapping(icu_data[0].domain, hwirq);

	handle_IRQ(irq, regs);

}



static asmlinkage void __exception_irq_entry

mmp2_handle_irq(struct pt_regs *regs)

{

	int irq, hwirq;



	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);

	if (!(hwirq & SEL_INT_PENDING))

		return;

	hwirq &= SEL_INT_NUM_MASK;

	irq = irq_find_mapping(icu_data[0].domain, hwirq);

	handle_IRQ(irq, regs);

}



/* MMP (ARMv5) */

void __init icu_init_irq(void)

{
@@ -212,6 +250,7 @@ void __init icu_init_irq(void) 
		set_irq_flags(irq, IRQF_VALID);

	}

	irq_set_default_host(icu_data[0].domain);

	set_handle_irq(mmp_handle_irq);

#ifdef CONFIG_CPU_PXA910

	icu_irq_chip.irq_set_wake = pxa910_set_wake;

#endif
@@ -318,144 +357,155 @@ void __init mmp2_init_icu(void) 
		set_irq_flags(irq, IRQF_VALID);

	}

	irq_set_default_host(icu_data[0].domain);

	set_handle_irq(mmp2_handle_irq);

#ifdef CONFIG_CPU_MMP2

	icu_irq_chip.irq_set_wake = mmp2_set_wake;

#endif

}



#ifdef CONFIG_OF

static const struct of_device_id intc_ids[] __initconst = {

	{ .compatible = "mrvl,mmp-intc", .data = &mmp_conf },

	{ .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },

	{}

};

static int __init mmp_init_bases(struct device_node *node)

{

	int ret, nr_irqs, irq, i = 0;



static const struct of_device_id mmp_mux_irq_match[] __initconst = {

	{ .compatible = "mrvl,mmp2-mux-intc" },

	{}

};

	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);

	if (ret) {

		pr_err("Not found mrvl,intc-nr-irqs property\n");

		return ret;

	}



	mmp_icu_base = of_iomap(node, 0);

	if (!mmp_icu_base) {

		pr_err("Failed to get interrupt controller register\n");

		return -ENOMEM;

	}



	icu_data[0].virq_base = 0;

	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,

						   &mmp_irq_domain_ops,

						   &icu_data[0]);

	for (irq = 0; irq < nr_irqs; irq++) {

		ret = irq_create_mapping(icu_data[0].domain, irq);

		if (!ret) {

			pr_err("Failed to mapping hwirq\n");

			goto err;

		}

		if (!irq)

			icu_data[0].virq_base = ret;

	}

	icu_data[0].nr_irqs = nr_irqs;

	return 0;

err:

	if (icu_data[0].virq_base) {

		for (i = 0; i < irq; i++)

			irq_dispose_mapping(icu_data[0].virq_base + i);

	}

	irq_domain_remove(icu_data[0].domain);

	iounmap(mmp_icu_base);

	return -EINVAL;

}



static int __init mmp_of_init(struct device_node *node,

			      struct device_node *parent)

{

	int ret;



int __init mmp2_mux_init(struct device_node *parent)

	ret = mmp_init_bases(node);

	if (ret < 0)

		return ret;



	icu_data[0].conf_enable = mmp_conf.conf_enable;

	icu_data[0].conf_disable = mmp_conf.conf_disable;

	icu_data[0].conf_mask = mmp_conf.conf_mask;

	irq_set_default_host(icu_data[0].domain);

	set_handle_irq(mmp_handle_irq);

	max_icu_nr = 1;

	return 0;

}

IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);



static int __init mmp2_of_init(struct device_node *node,

			       struct device_node *parent)

{

	int ret;



	ret = mmp_init_bases(node);

	if (ret < 0)

		return ret;



	icu_data[0].conf_enable = mmp2_conf.conf_enable;

	icu_data[0].conf_disable = mmp2_conf.conf_disable;

	icu_data[0].conf_mask = mmp2_conf.conf_mask;

	irq_set_default_host(icu_data[0].domain);

	set_handle_irq(mmp2_handle_irq);

	max_icu_nr = 1;

	return 0;

}

IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);



static int __init mmp2_mux_of_init(struct device_node *node,

				   struct device_node *parent)

{

	struct device_node *node;

	const struct of_device_id *of_id;

	struct resource res;

	int i, irq_base, ret, irq;

	int i, ret, irq, j = 0;

	u32 nr_irqs, mfp_irq;



	node = parent;

	max_icu_nr = 1;

	for (i = 1; i < MAX_ICU_NR; i++) {

		node = of_find_matching_node(node, mmp_mux_irq_match);

		if (!node)

			break;

		of_id = of_match_node(&mmp_mux_irq_match[0], node);

	if (!parent)

		return -ENODEV;



	i = max_icu_nr;

	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",

				   &nr_irqs);

	if (ret) {

		pr_err("Not found mrvl,intc-nr-irqs property\n");

			ret = -EINVAL;

			goto err;

		return -EINVAL;

	}

	ret = of_address_to_resource(node, 0, &res);

	if (ret < 0) {

		pr_err("Not found reg property\n");

			ret = -EINVAL;

			goto err;

		return -EINVAL;

	}

	icu_data[i].reg_status = mmp_icu_base + res.start;

	ret = of_address_to_resource(node, 1, &res);

	if (ret < 0) {

		pr_err("Not found reg property\n");

			ret = -EINVAL;

			goto err;

		return -EINVAL;

	}

	icu_data[i].reg_mask = mmp_icu_base + res.start;

	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);

		if (!icu_data[i].cascade_irq) {

			ret = -EINVAL;

			goto err;

		}

	if (!icu_data[i].cascade_irq)

		return -EINVAL;



		irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);

		if (irq_base < 0) {

			pr_err("Failed to allocate IRQ numbers for mux intc\n");

			ret = irq_base;

	icu_data[i].virq_base = 0;

	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,

						   &mmp_irq_domain_ops,

						   &icu_data[i]);

	for (irq = 0; irq < nr_irqs; irq++) {

		ret = irq_create_mapping(icu_data[i].domain, irq);

		if (!ret) {

			pr_err("Failed to mapping hwirq\n");

			goto err;

		}

		if (!irq)

			icu_data[i].virq_base = ret;

	}

	icu_data[i].nr_irqs = nr_irqs;

	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",

				  &mfp_irq)) {

			icu_data[i].clr_mfp_irq_base = irq_base;

		icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;

		icu_data[i].clr_mfp_hwirq = mfp_irq;

	}

	irq_set_chained_handler(icu_data[i].cascade_irq,

				icu_mux_irq_demux);

		icu_data[i].nr_irqs = nr_irqs;

		icu_data[i].virq_base = irq_base;

		icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,

							   irq_base, 0,

							   &mmp_irq_domain_ops,

							   &icu_data[i]);

		for (irq = irq_base; irq < irq_base + nr_irqs; irq++)

			icu_mask_irq(irq_get_irq_data(irq));

	}

	max_icu_nr = i;

	max_icu_nr++;

	return 0;

err:

	of_node_put(node);

	max_icu_nr = i;

	return ret;

	if (icu_data[i].virq_base) {

		for (j = 0; j < irq; j++)

			irq_dispose_mapping(icu_data[i].virq_base + j);

	}



void __init mmp_dt_irq_init(void)

{

	struct device_node *node;

	const struct of_device_id *of_id;

	struct mmp_intc_conf *conf;

	int nr_irqs, irq_base, ret, irq;



	node = of_find_matching_node(NULL, intc_ids);

	if (!node) {

		pr_err("Failed to find interrupt controller in arch-mmp\n");

		return;

	}

	of_id = of_match_node(intc_ids, node);

	conf = of_id->data;



	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);

	if (ret) {

		pr_err("Not found mrvl,intc-nr-irqs property\n");

		return;

	}



	mmp_icu_base = of_iomap(node, 0);

	if (!mmp_icu_base) {

		pr_err("Failed to get interrupt controller register\n");

		return;

	}



	irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);

	if (irq_base < 0) {

		pr_err("Failed to allocate IRQ numbers\n");

		goto err;

	} else if (irq_base != NR_IRQS_LEGACY) {

		pr_err("ICU's irqbase should be started from 0\n");

		goto err;

	}

	icu_data[0].conf_enable = conf->conf_enable;

	icu_data[0].conf_disable = conf->conf_disable;

	icu_data[0].conf_mask = conf->conf_mask;

	icu_data[0].nr_irqs = nr_irqs;

	icu_data[0].virq_base = 0;

	icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,

						   &mmp_irq_domain_ops,

						   &icu_data[0]);

	irq_set_default_host(icu_data[0].domain);

	for (irq = 0; irq < nr_irqs; irq++)

		icu_mask_irq(irq_get_irq_data(irq));

	mmp2_mux_init(node);

	return;

err:

	iounmap(mmp_icu_base);

	irq_domain_remove(icu_data[i].domain);

	return -EINVAL;

}

IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);

#endif